derek.holloway
7502bf64a4
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214 lines
14 KiB
LLVM
214 lines
14 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
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; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve,+sme,+sme2p1 -stop-before=finalize-isel -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK-BEFORE-ISEL
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; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve,+sme,+sme2p1 -stop-after=finalize-isel -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK-AFTER-ISEL
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target triple = "aarch64-unknown-linux-gnu"
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declare void @bar_enabled(<vscale x 4 x i32>) #0
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declare void @bar(<vscale x 4 x i32>)
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declare <vscale x 4 x i32> @bar_retv_enabled() #0
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declare <vscale x 4 x i32> @bar_retv()
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; Non-streaming -> calls streaming callee
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define void @foo_non_streaming_pass_arg(ptr %arg) {
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; CHECK-BEFORE-ISEL-LABEL: name: foo_non_streaming_pass_arg
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; CHECK-BEFORE-ISEL: bb.0.entry:
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; CHECK-BEFORE-ISEL-NEXT: liveins: $x0
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; CHECK-BEFORE-ISEL-NEXT: {{ $}}
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; CHECK-BEFORE-ISEL-NEXT: [[COPY:%[0-9]+]]:gpr64common = COPY $x0
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; CHECK-BEFORE-ISEL-NEXT: [[LDR_ZXI:%[0-9]+]]:zpr = LDR_ZXI [[COPY]], 0 :: (load (<vscale x 1 x s128>) from %ir.arg)
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; CHECK-BEFORE-ISEL-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
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; CHECK-BEFORE-ISEL-NEXT: CHECK_MATCHING_VL_PSEUDO
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; CHECK-BEFORE-ISEL-NEXT: MSRpstatesvcrImm1 1, 1, csr_aarch64_smstartstop, implicit-def dead $nzcv, implicit-def $sp, implicit-def $z0, implicit $vg, implicit-def $vg, implicit-def $fpmr
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; CHECK-BEFORE-ISEL-NEXT: $z0 = COPY [[LDR_ZXI]]
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; CHECK-BEFORE-ISEL-NEXT: BL @bar_enabled, csr_aarch64_sve_aapcs, implicit-def dead $lr, implicit $sp, implicit $z0, implicit-def $sp
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; CHECK-BEFORE-ISEL-NEXT: ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
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; CHECK-BEFORE-ISEL-NEXT: MSRpstatesvcrImm1 1, 0, csr_aarch64_smstartstop, implicit-def dead $nzcv, implicit $vg, implicit-def $vg, implicit-def $fpmr
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; CHECK-BEFORE-ISEL-NEXT: RET_ReallyLR
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;
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; CHECK-AFTER-ISEL-LABEL: name: foo_non_streaming_pass_arg
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; CHECK-AFTER-ISEL: bb.0.entry:
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; CHECK-AFTER-ISEL-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
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; CHECK-AFTER-ISEL-NEXT: liveins: $x0
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; CHECK-AFTER-ISEL-NEXT: {{ $}}
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; CHECK-AFTER-ISEL-NEXT: [[COPY:%[0-9]+]]:gpr64common = COPY $x0
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; CHECK-AFTER-ISEL-NEXT: [[LDR_ZXI:%[0-9]+]]:zpr = LDR_ZXI [[COPY]], 0 :: (load (<vscale x 1 x s128>) from %ir.arg)
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; CHECK-AFTER-ISEL-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
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; CHECK-AFTER-ISEL-NEXT: [[RDVLI_XI:%[0-9]+]]:gpr64 = RDVLI_XI 1, implicit $vg
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; CHECK-AFTER-ISEL-NEXT: [[COPY1:%[0-9]+]]:gpr64sp = COPY [[RDVLI_XI]]
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; CHECK-AFTER-ISEL-NEXT: [[ADDSVL_XXI:%[0-9]+]]:gpr64sp = ADDSVL_XXI [[COPY1]], -1, implicit $vg
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; CHECK-AFTER-ISEL-NEXT: [[COPY2:%[0-9]+]]:gpr64 = COPY [[ADDSVL_XXI]]
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; CHECK-AFTER-ISEL-NEXT: CBZX [[COPY2]], %bb.2
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; CHECK-AFTER-ISEL-NEXT: {{ $}}
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; CHECK-AFTER-ISEL-NEXT: bb.1.entry:
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; CHECK-AFTER-ISEL-NEXT: successors:
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; CHECK-AFTER-ISEL-NEXT: {{ $}}
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; CHECK-AFTER-ISEL-NEXT: BRK 1
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; CHECK-AFTER-ISEL-NEXT: {{ $}}
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; CHECK-AFTER-ISEL-NEXT: bb.2.entry:
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; CHECK-AFTER-ISEL-NEXT: MSRpstatesvcrImm1 1, 1, csr_aarch64_smstartstop, implicit-def dead $nzcv, implicit-def $sp, implicit-def $z0, implicit $vg, implicit-def $vg, implicit-def $fpmr
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; CHECK-AFTER-ISEL-NEXT: $z0 = COPY [[LDR_ZXI]]
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; CHECK-AFTER-ISEL-NEXT: BL @bar_enabled, csr_aarch64_sve_aapcs, implicit-def dead $lr, implicit $sp, implicit $z0, implicit-def $sp
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; CHECK-AFTER-ISEL-NEXT: ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
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; CHECK-AFTER-ISEL-NEXT: MSRpstatesvcrImm1 1, 0, csr_aarch64_smstartstop, implicit-def dead $nzcv, implicit $vg, implicit-def $vg, implicit-def $fpmr
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; CHECK-AFTER-ISEL-NEXT: RET_ReallyLR
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entry:
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%v = load <vscale x 4 x i32>, ptr %arg, align 16
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tail call void @bar_enabled(<vscale x 4 x i32> %v) #0
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ret void
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}
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; Streaming -> calls non-streaming callee
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define void @foo_streaming_pass_arg(ptr %arg) #0 {
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; CHECK-BEFORE-ISEL-LABEL: name: foo_streaming_pass_arg
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; CHECK-BEFORE-ISEL: bb.0.entry:
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; CHECK-BEFORE-ISEL-NEXT: liveins: $x0
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; CHECK-BEFORE-ISEL-NEXT: {{ $}}
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; CHECK-BEFORE-ISEL-NEXT: [[COPY:%[0-9]+]]:gpr64common = COPY $x0
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; CHECK-BEFORE-ISEL-NEXT: [[LDR_ZXI:%[0-9]+]]:zpr = LDR_ZXI [[COPY]], 0 :: (load (<vscale x 1 x s128>) from %ir.arg)
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; CHECK-BEFORE-ISEL-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
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; CHECK-BEFORE-ISEL-NEXT: MSRpstatesvcrImm1 1, 0, csr_aarch64_smstartstop, implicit-def dead $nzcv, implicit-def $sp, implicit-def $z0, implicit $vg, implicit-def $vg, implicit-def $fpmr
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; CHECK-BEFORE-ISEL-NEXT: CHECK_MATCHING_VL_PSEUDO
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; CHECK-BEFORE-ISEL-NEXT: $z0 = COPY [[LDR_ZXI]]
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; CHECK-BEFORE-ISEL-NEXT: BL @bar, csr_aarch64_sve_aapcs, implicit-def dead $lr, implicit $sp, implicit $z0, implicit-def $sp
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; CHECK-BEFORE-ISEL-NEXT: ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
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; CHECK-BEFORE-ISEL-NEXT: MSRpstatesvcrImm1 1, 1, csr_aarch64_smstartstop, implicit-def dead $nzcv, implicit $vg, implicit-def $vg, implicit-def $fpmr
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; CHECK-BEFORE-ISEL-NEXT: RET_ReallyLR
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;
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; CHECK-AFTER-ISEL-LABEL: name: foo_streaming_pass_arg
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; CHECK-AFTER-ISEL: bb.0.entry:
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; CHECK-AFTER-ISEL-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
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; CHECK-AFTER-ISEL-NEXT: liveins: $x0
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; CHECK-AFTER-ISEL-NEXT: {{ $}}
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; CHECK-AFTER-ISEL-NEXT: [[COPY:%[0-9]+]]:gpr64common = COPY $x0
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; CHECK-AFTER-ISEL-NEXT: [[LDR_ZXI:%[0-9]+]]:zpr = LDR_ZXI [[COPY]], 0 :: (load (<vscale x 1 x s128>) from %ir.arg)
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; CHECK-AFTER-ISEL-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
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; CHECK-AFTER-ISEL-NEXT: MSRpstatesvcrImm1 1, 0, csr_aarch64_smstartstop, implicit-def dead $nzcv, implicit-def $sp, implicit-def $z0, implicit $vg, implicit-def $vg, implicit-def $fpmr
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; CHECK-AFTER-ISEL-NEXT: [[RDVLI_XI:%[0-9]+]]:gpr64 = RDVLI_XI 1, implicit $vg
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; CHECK-AFTER-ISEL-NEXT: [[COPY1:%[0-9]+]]:gpr64sp = COPY [[RDVLI_XI]]
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; CHECK-AFTER-ISEL-NEXT: [[ADDSVL_XXI:%[0-9]+]]:gpr64sp = ADDSVL_XXI [[COPY1]], -1, implicit $vg
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; CHECK-AFTER-ISEL-NEXT: [[COPY2:%[0-9]+]]:gpr64 = COPY [[ADDSVL_XXI]]
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; CHECK-AFTER-ISEL-NEXT: CBZX [[COPY2]], %bb.2
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; CHECK-AFTER-ISEL-NEXT: {{ $}}
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; CHECK-AFTER-ISEL-NEXT: bb.1.entry:
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; CHECK-AFTER-ISEL-NEXT: successors:
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; CHECK-AFTER-ISEL-NEXT: {{ $}}
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; CHECK-AFTER-ISEL-NEXT: BRK 1
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; CHECK-AFTER-ISEL-NEXT: {{ $}}
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; CHECK-AFTER-ISEL-NEXT: bb.2.entry:
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; CHECK-AFTER-ISEL-NEXT: $z0 = COPY [[LDR_ZXI]]
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; CHECK-AFTER-ISEL-NEXT: BL @bar, csr_aarch64_sve_aapcs, implicit-def dead $lr, implicit $sp, implicit $z0, implicit-def $sp
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; CHECK-AFTER-ISEL-NEXT: ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
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; CHECK-AFTER-ISEL-NEXT: MSRpstatesvcrImm1 1, 1, csr_aarch64_smstartstop, implicit-def dead $nzcv, implicit $vg, implicit-def $vg, implicit-def $fpmr
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; CHECK-AFTER-ISEL-NEXT: RET_ReallyLR
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entry:
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%v = load <vscale x 4 x i32>, ptr %arg, align 16
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tail call void @bar(<vscale x 4 x i32> %v)
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ret void
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}
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; Non-streaming -> returns SVE value from streaming callee
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define void @foo_non_streaming_retval(ptr %ptr) {
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; CHECK-BEFORE-ISEL-LABEL: name: foo_non_streaming_retval
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; CHECK-BEFORE-ISEL: bb.0.entry:
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; CHECK-BEFORE-ISEL-NEXT: liveins: $x0
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; CHECK-BEFORE-ISEL-NEXT: {{ $}}
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; CHECK-BEFORE-ISEL-NEXT: [[COPY:%[0-9]+]]:gpr64common = COPY $x0
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; CHECK-BEFORE-ISEL-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
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; CHECK-BEFORE-ISEL-NEXT: CHECK_MATCHING_VL_PSEUDO
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; CHECK-BEFORE-ISEL-NEXT: MSRpstatesvcrImm1 1, 1, csr_aarch64_smstartstop, implicit-def dead $nzcv, implicit-def $sp, implicit-def $z0, implicit $vg, implicit-def $vg, implicit-def $fpmr
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; CHECK-BEFORE-ISEL-NEXT: BL @bar_retv_enabled, csr_aarch64_sve_aapcs, implicit-def dead $lr, implicit $sp, implicit-def $sp, implicit-def $z0
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; CHECK-BEFORE-ISEL-NEXT: ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
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; CHECK-BEFORE-ISEL-NEXT: [[COPY1:%[0-9]+]]:zpr = COPY $z0
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; CHECK-BEFORE-ISEL-NEXT: MSRpstatesvcrImm1 1, 0, csr_aarch64_smstartstop, implicit-def dead $nzcv, implicit $vg, implicit-def $vg, implicit-def $fpmr
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; CHECK-BEFORE-ISEL-NEXT: [[COPY2:%[0-9]+]]:zpr = COPY [[COPY1]]
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; CHECK-BEFORE-ISEL-NEXT: STR_ZXI [[COPY2]], [[COPY]], 0 :: (store (<vscale x 1 x s128>) into %ir.ptr)
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; CHECK-BEFORE-ISEL-NEXT: RET_ReallyLR
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;
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; CHECK-AFTER-ISEL-LABEL: name: foo_non_streaming_retval
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; CHECK-AFTER-ISEL: bb.0.entry:
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; CHECK-AFTER-ISEL-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
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; CHECK-AFTER-ISEL-NEXT: liveins: $x0
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; CHECK-AFTER-ISEL-NEXT: {{ $}}
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; CHECK-AFTER-ISEL-NEXT: [[COPY:%[0-9]+]]:gpr64common = COPY $x0
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; CHECK-AFTER-ISEL-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
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; CHECK-AFTER-ISEL-NEXT: [[RDVLI_XI:%[0-9]+]]:gpr64 = RDVLI_XI 1, implicit $vg
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; CHECK-AFTER-ISEL-NEXT: [[COPY1:%[0-9]+]]:gpr64sp = COPY [[RDVLI_XI]]
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; CHECK-AFTER-ISEL-NEXT: [[ADDSVL_XXI:%[0-9]+]]:gpr64sp = ADDSVL_XXI [[COPY1]], -1, implicit $vg
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; CHECK-AFTER-ISEL-NEXT: [[COPY2:%[0-9]+]]:gpr64 = COPY [[ADDSVL_XXI]]
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; CHECK-AFTER-ISEL-NEXT: CBZX [[COPY2]], %bb.2
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; CHECK-AFTER-ISEL-NEXT: {{ $}}
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; CHECK-AFTER-ISEL-NEXT: bb.1.entry:
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; CHECK-AFTER-ISEL-NEXT: successors:
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; CHECK-AFTER-ISEL-NEXT: {{ $}}
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; CHECK-AFTER-ISEL-NEXT: BRK 1
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; CHECK-AFTER-ISEL-NEXT: {{ $}}
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; CHECK-AFTER-ISEL-NEXT: bb.2.entry:
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; CHECK-AFTER-ISEL-NEXT: MSRpstatesvcrImm1 1, 1, csr_aarch64_smstartstop, implicit-def dead $nzcv, implicit-def $sp, implicit-def $z0, implicit $vg, implicit-def $vg, implicit-def $fpmr
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; CHECK-AFTER-ISEL-NEXT: BL @bar_retv_enabled, csr_aarch64_sve_aapcs, implicit-def dead $lr, implicit $sp, implicit-def $sp, implicit-def $z0
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; CHECK-AFTER-ISEL-NEXT: ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
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; CHECK-AFTER-ISEL-NEXT: [[COPY3:%[0-9]+]]:zpr = COPY $z0
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; CHECK-AFTER-ISEL-NEXT: MSRpstatesvcrImm1 1, 0, csr_aarch64_smstartstop, implicit-def dead $nzcv, implicit $vg, implicit-def $vg, implicit-def $fpmr
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; CHECK-AFTER-ISEL-NEXT: [[COPY4:%[0-9]+]]:zpr = COPY [[COPY3]]
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; CHECK-AFTER-ISEL-NEXT: STR_ZXI [[COPY4]], [[COPY]], 0 :: (store (<vscale x 1 x s128>) into %ir.ptr)
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; CHECK-AFTER-ISEL-NEXT: RET_ReallyLR
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entry:
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%v = tail call <vscale x 4 x i32> @bar_retv_enabled() #0
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store <vscale x 4 x i32> %v, ptr %ptr, align 16
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ret void
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}
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; Streaming -> returns SVE value from non-streaming callee
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define void @foo_streaming_retval(ptr %ptr) #0 {
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; CHECK-BEFORE-ISEL-LABEL: name: foo_streaming_retval
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; CHECK-BEFORE-ISEL: bb.0.entry:
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; CHECK-BEFORE-ISEL-NEXT: liveins: $x0
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; CHECK-BEFORE-ISEL-NEXT: {{ $}}
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; CHECK-BEFORE-ISEL-NEXT: [[COPY:%[0-9]+]]:gpr64common = COPY $x0
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; CHECK-BEFORE-ISEL-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
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; CHECK-BEFORE-ISEL-NEXT: MSRpstatesvcrImm1 1, 0, csr_aarch64_smstartstop, implicit-def dead $nzcv, implicit-def $sp, implicit-def $z0, implicit $vg, implicit-def $vg, implicit-def $fpmr
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; CHECK-BEFORE-ISEL-NEXT: CHECK_MATCHING_VL_PSEUDO
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; CHECK-BEFORE-ISEL-NEXT: BL @bar_retv, csr_aarch64_sve_aapcs, implicit-def dead $lr, implicit $sp, implicit-def $sp, implicit-def $z0
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; CHECK-BEFORE-ISEL-NEXT: ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
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; CHECK-BEFORE-ISEL-NEXT: [[COPY1:%[0-9]+]]:zpr = COPY $z0
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; CHECK-BEFORE-ISEL-NEXT: MSRpstatesvcrImm1 1, 1, csr_aarch64_smstartstop, implicit-def dead $nzcv, implicit $vg, implicit-def $vg, implicit-def $fpmr
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; CHECK-BEFORE-ISEL-NEXT: [[COPY2:%[0-9]+]]:zpr = COPY [[COPY1]]
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; CHECK-BEFORE-ISEL-NEXT: STR_ZXI [[COPY2]], [[COPY]], 0 :: (store (<vscale x 1 x s128>) into %ir.ptr)
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; CHECK-BEFORE-ISEL-NEXT: RET_ReallyLR
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;
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; CHECK-AFTER-ISEL-LABEL: name: foo_streaming_retval
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; CHECK-AFTER-ISEL: bb.0.entry:
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; CHECK-AFTER-ISEL-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
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; CHECK-AFTER-ISEL-NEXT: liveins: $x0
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; CHECK-AFTER-ISEL-NEXT: {{ $}}
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; CHECK-AFTER-ISEL-NEXT: [[COPY:%[0-9]+]]:gpr64common = COPY $x0
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; CHECK-AFTER-ISEL-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
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; CHECK-AFTER-ISEL-NEXT: MSRpstatesvcrImm1 1, 0, csr_aarch64_smstartstop, implicit-def dead $nzcv, implicit-def $sp, implicit-def $z0, implicit $vg, implicit-def $vg, implicit-def $fpmr
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; CHECK-AFTER-ISEL-NEXT: [[RDVLI_XI:%[0-9]+]]:gpr64 = RDVLI_XI 1, implicit $vg
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; CHECK-AFTER-ISEL-NEXT: [[COPY1:%[0-9]+]]:gpr64sp = COPY [[RDVLI_XI]]
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; CHECK-AFTER-ISEL-NEXT: [[ADDSVL_XXI:%[0-9]+]]:gpr64sp = ADDSVL_XXI [[COPY1]], -1, implicit $vg
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; CHECK-AFTER-ISEL-NEXT: [[COPY2:%[0-9]+]]:gpr64 = COPY [[ADDSVL_XXI]]
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; CHECK-AFTER-ISEL-NEXT: CBZX [[COPY2]], %bb.2
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; CHECK-AFTER-ISEL-NEXT: {{ $}}
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; CHECK-AFTER-ISEL-NEXT: bb.1.entry:
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; CHECK-AFTER-ISEL-NEXT: successors:
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; CHECK-AFTER-ISEL-NEXT: {{ $}}
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; CHECK-AFTER-ISEL-NEXT: BRK 1
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; CHECK-AFTER-ISEL-NEXT: {{ $}}
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; CHECK-AFTER-ISEL-NEXT: bb.2.entry:
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; CHECK-AFTER-ISEL-NEXT: BL @bar_retv, csr_aarch64_sve_aapcs, implicit-def dead $lr, implicit $sp, implicit-def $sp, implicit-def $z0
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; CHECK-AFTER-ISEL-NEXT: ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
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; CHECK-AFTER-ISEL-NEXT: [[COPY3:%[0-9]+]]:zpr = COPY $z0
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; CHECK-AFTER-ISEL-NEXT: MSRpstatesvcrImm1 1, 1, csr_aarch64_smstartstop, implicit-def dead $nzcv, implicit $vg, implicit-def $vg, implicit-def $fpmr
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; CHECK-AFTER-ISEL-NEXT: [[COPY4:%[0-9]+]]:zpr = COPY [[COPY3]]
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; CHECK-AFTER-ISEL-NEXT: STR_ZXI [[COPY4]], [[COPY]], 0 :: (store (<vscale x 1 x s128>) into %ir.ptr)
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; CHECK-AFTER-ISEL-NEXT: RET_ReallyLR
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entry:
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%v = tail call <vscale x 4 x i32> @bar_retv()
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store <vscale x 4 x i32> %v, ptr %ptr, align 16
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ret void
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}
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attributes #0 = { "aarch64_pstate_sm_enabled" }
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attributes #1 = { "aarch64_pstate_sm_compatible" }
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