derek.holloway
7502bf64a4
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290 lines
16 KiB
LLVM
290 lines
16 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --filter-out "// kill:" --version 4
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; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme-f8f16,+sme-f8f32 -force-streaming < %s | FileCheck %s
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; FMLAL (indexed)
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define void @test_fmlal_vg2x1(i32 %slice, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) {
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; CHECK-LABEL: test_fmlal_vg2x1:
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; CHECK: // %bb.0:
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; CHECK: mov w8, w0
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; CHECK: fmlal za.h[w8, 0:1], z0.b, z1.b[0]
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; CHECK: fmlal za.h[w8, 14:15], z0.b, z1.b[15]
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; CHECK: ret
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call void @llvm.aarch64.sme.fp8.fmlal.lane.za16.vg2x1(i32 %slice,
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<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm,
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i32 0)
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%add = add i32 %slice, 14
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call void @llvm.aarch64.sme.fp8.fmlal.lane.za16.vg2x1(i32 %add,
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<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm,
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i32 15)
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ret void
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}
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define void @test_fmlal_vg2x2(i32 %slice, <vscale x 16 x i8> %zn0, <vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zm) {
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; CHECK-LABEL: test_fmlal_vg2x2:
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; CHECK: // %bb.0:
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; CHECK: mov w8, w0
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; CHECK: fmlal za.h[w8, 0:1, vgx2], { z0.b, z1.b }, z2.b[0]
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; CHECK: fmlal za.h[w8, 6:7, vgx2], { z0.b, z1.b }, z2.b[15]
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; CHECK: ret
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call void @llvm.aarch64.sme.fp8.fmlal.lane.za16.vg2x2(i32 %slice,
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<vscale x 16 x i8> %zn0, <vscale x 16 x i8> %zn1,
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<vscale x 16 x i8> %zm,
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i32 0)
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%add = add i32 %slice, 6
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call void @llvm.aarch64.sme.fp8.fmlal.lane.za16.vg2x2(i32 %add,
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<vscale x 16 x i8> %zn0, <vscale x 16 x i8> %zn1,
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<vscale x 16 x i8> %zm,
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i32 15)
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ret void
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}
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define void @test_fmlal_vg2x4(i32 %slice, <vscale x 16 x i8> %zn0, <vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zn2, <vscale x 16 x i8> %zn3, <vscale x 16 x i8> %zm) {
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; CHECK-LABEL: test_fmlal_vg2x4:
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; CHECK: // %bb.0:
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; CHECK: mov w8, w0
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; CHECK: fmlal za.h[w8, 0:1, vgx4], { z0.b - z3.b }, z4.b[0]
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; CHECK: fmlal za.h[w8, 6:7, vgx4], { z0.b - z3.b }, z4.b[15]
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; CHECK: ret
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call void @llvm.aarch64.sme.fp8.fmlal.lane.za16.vg2x4(i32 %slice,
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<vscale x 16 x i8> %zn0, <vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zn2, <vscale x 16 x i8> %zn3,
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<vscale x 16 x i8> %zm,
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i32 0)
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%add = add i32 %slice, 6
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call void @llvm.aarch64.sme.fp8.fmlal.lane.za16.vg2x4(i32 %add,
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<vscale x 16 x i8> %zn0, <vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zn2, <vscale x 16 x i8> %zn3,
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<vscale x 16 x i8> %zm,
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i32 15)
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ret void
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}
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; FMLALL (indexed)
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define void @test_fmlall_vg4x1(i32 %slice, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) {
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; CHECK-LABEL: test_fmlall_vg4x1:
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; CHECK: // %bb.0:
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; CHECK: mov w8, w0
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; CHECK: fmlall za.s[w8, 0:3], z0.b, z1.b[0]
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; CHECK: fmlall za.s[w8, 12:15], z0.b, z1.b[15]
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; CHECK: ret
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call void @llvm.aarch64.sme.fp8.fmlall.lane.za32.vg4x1(i32 %slice,
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<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm,
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i32 0)
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%add = add i32 %slice, 12
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call void @llvm.aarch64.sme.fp8.fmlall.lane.za32.vg4x1(i32 %add,
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<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm,
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i32 15)
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ret void
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}
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define void @test_fmlall_vg4x2(i32 %slice, <vscale x 16 x i8> %zn0, <vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zm) {
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; CHECK-LABEL: test_fmlall_vg4x2:
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; CHECK: // %bb.0:
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; CHECK: mov w8, w0
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; CHECK: fmlall za.s[w8, 0:3, vgx2], { z0.b, z1.b }, z2.b[0]
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; CHECK: fmlall za.s[w8, 4:7, vgx2], { z0.b, z1.b }, z2.b[15]
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; CHECK: ret
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call void @llvm.aarch64.sme.fp8.fmlall.lane.za32.vg4x2(i32 %slice,
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<vscale x 16 x i8> %zn0, <vscale x 16 x i8> %zn1,
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<vscale x 16 x i8> %zm,
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i32 0)
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%add = add i32 %slice, 4
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call void @llvm.aarch64.sme.fp8.fmlall.lane.za32.vg4x2(i32 %add,
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<vscale x 16 x i8> %zn0, <vscale x 16 x i8> %zn1,
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<vscale x 16 x i8> %zm,
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i32 15)
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ret void
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}
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define void @test_fmlall_vg4x4(i32 %slice, <vscale x 16 x i8> %zn0, <vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zn2, <vscale x 16 x i8> %zn3, <vscale x 16 x i8> %zm) {
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; CHECK-LABEL: test_fmlall_vg4x4:
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; CHECK: // %bb.0:
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; CHECK: mov w8, w0
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; CHECK: fmlall za.s[w8, 0:3, vgx4], { z0.b - z3.b }, z4.b[8]
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; CHECK: fmlall za.s[w8, 4:7, vgx4], { z0.b - z3.b }, z4.b[15]
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; CHECK: ret
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call void @llvm.aarch64.sme.fp8.fmlall.lane.za32.vg4x4(i32 %slice,
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<vscale x 16 x i8> %zn0, <vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zn2, <vscale x 16 x i8> %zn3,
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<vscale x 16 x i8> %zm,
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i32 8)
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%add = add i32 %slice, 4
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call void @llvm.aarch64.sme.fp8.fmlall.lane.za32.vg4x4(i32 %add,
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<vscale x 16 x i8> %zn0, <vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zn2, <vscale x 16 x i8> %zn3,
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<vscale x 16 x i8> %zm,
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i32 15)
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ret void
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}
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; FMLAL (single)
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define void @test_fmlal_single_vg2x1(i32 %slice, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) {
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; CHECK-LABEL: test_fmlal_single_vg2x1:
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; CHECK: // %bb.0:
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; CHECK: mov w8, w0
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; CHECK: fmlal za.h[w8, 0:1], z0.b, z1.b
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; CHECK: fmlal za.h[w8, 14:15], z0.b, z1.b
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; CHECK: ret
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call void @llvm.aarch64.sme.fp8.fmlal.za16.vg2x1(i32 %slice, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm)
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%add = add i32 %slice, 14
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call void @llvm.aarch64.sme.fp8.fmlal.za16.vg2x1(i32 %add, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm)
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ret void
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}
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define void @test_fmlal_single_vg2x2(i32 %slice, <vscale x 16 x i8> %zn0, <vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zm) {
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; CHECK-LABEL: test_fmlal_single_vg2x2:
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; CHECK: // %bb.0:
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; CHECK: mov w8, w0
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; CHECK: fmlal za.h[w8, 0:1, vgx2], { z0.b, z1.b }, z2.b
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; CHECK: fmlal za.h[w8, 6:7, vgx2], { z0.b, z1.b }, z2.b
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; CHECK: ret
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call void @llvm.aarch64.sme.fp8.fmlal.single.za16.vg2x2(i32 %slice,
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<vscale x 16 x i8> %zn0, <vscale x 16 x i8> %zn1,
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<vscale x 16 x i8> %zm)
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%add = add i32 %slice, 6
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call void @llvm.aarch64.sme.fp8.fmlal.single.za16.vg2x2(i32 %add,
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<vscale x 16 x i8> %zn0, <vscale x 16 x i8> %zn1,
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<vscale x 16 x i8> %zm)
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ret void
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}
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define void @test_fmlal_single_vg2x4(i32 %slice, <vscale x 16 x i8> %zn0, <vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zn2, <vscale x 16 x i8> %zn3, <vscale x 16 x i8> %zm) {
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; CHECK-LABEL: test_fmlal_single_vg2x4:
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; CHECK: // %bb.0:
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; CHECK: mov w8, w0
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; CHECK: fmlal za.h[w8, 0:1, vgx4], { z0.b - z3.b }, z4.b
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; CHECK: fmlal za.h[w8, 6:7, vgx4], { z0.b - z3.b }, z4.b
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; CHECK: ret
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call void @llvm.aarch64.sme.fp8.fmlal.single.za16.vg2x4(i32 %slice,
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<vscale x 16 x i8> %zn0, <vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zn2, <vscale x 16 x i8> %zn3,
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<vscale x 16 x i8> %zm)
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%add = add i32 %slice, 6
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call void @llvm.aarch64.sme.fp8.fmlal.single.za16.vg2x4(i32 %add,
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<vscale x 16 x i8> %zn0, <vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zn2, <vscale x 16 x i8> %zn3,
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<vscale x 16 x i8> %zm)
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ret void
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}
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; FMLALL (single)
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define void @test_fmlall_single_vg4x1(i32 %slice, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) {
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; CHECK-LABEL: test_fmlall_single_vg4x1:
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; CHECK: // %bb.0:
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; CHECK: mov w8, w0
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; CHECK: fmlall za.s[w8, 0:3], z0.b, z1.b
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; CHECK: fmlall za.s[w8, 12:15], z0.b, z1.b
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; CHECK: ret
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call void @llvm.aarch64.sme.fp8.fmlall.za32.vg4x1(i32 %slice, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm)
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%add = add i32 %slice, 12
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call void @llvm.aarch64.sme.fp8.fmlall.za32.vg4x1(i32 %add, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm)
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ret void
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}
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define void @test_fmlall_single_vg4x2(i32 %slice, <vscale x 16 x i8> %zn0, <vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zm) {
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; CHECK-LABEL: test_fmlall_single_vg4x2:
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; CHECK: // %bb.0:
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; CHECK: mov w8, w0
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; CHECK: fmlall za.s[w8, 0:3, vgx2], { z0.b, z1.b }, z2.b
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; CHECK: fmlall za.s[w8, 4:7, vgx2], { z0.b, z1.b }, z2.b
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; CHECK: ret
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call void @llvm.aarch64.sme.fp8.fmlall.single.za32.vg4x2(i32 %slice,
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<vscale x 16 x i8> %zn0, <vscale x 16 x i8> %zn1,
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<vscale x 16 x i8> %zm)
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%add = add i32 %slice, 4
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call void @llvm.aarch64.sme.fp8.fmlall.single.za32.vg4x2(i32 %add,
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<vscale x 16 x i8> %zn0, <vscale x 16 x i8> %zn1,
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<vscale x 16 x i8> %zm)
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ret void
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}
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define void @test_fmlall_single_vg4x4(i32 %slice, <vscale x 16 x i8> %zn0, <vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zn2, <vscale x 16 x i8> %zn3, <vscale x 16 x i8> %zm) {
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; CHECK-LABEL: test_fmlall_single_vg4x4:
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; CHECK: // %bb.0:
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; CHECK: mov w8, w0
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; CHECK: fmlall za.s[w8, 0:3, vgx4], { z0.b - z3.b }, z4.b
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; CHECK: fmlall za.s[w8, 4:7, vgx4], { z0.b - z3.b }, z4.b
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; CHECK: ret
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call void @llvm.aarch64.sme.fp8.fmlall.single.za32.vg4x4(i32 %slice,
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<vscale x 16 x i8> %zn0, <vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zn2, <vscale x 16 x i8> %zn3,
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<vscale x 16 x i8> %zm)
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%add = add i32 %slice, 4
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call void @llvm.aarch64.sme.fp8.fmlall.single.za32.vg4x4(i32 %add,
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<vscale x 16 x i8> %zn0, <vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zn2, <vscale x 16 x i8> %zn3,
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<vscale x 16 x i8> %zm)
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ret void
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}
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; FMLAL (multi)
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define void @test_fmlal_multi_vg2x2(i32 %slice, <vscale x 16 x i8> %zn0, <vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zm0, <vscale x 16 x i8> %zm1) {
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; CHECK-LABEL: test_fmlal_multi_vg2x2:
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; CHECK: // %bb.0:
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; CHECK: mov w8, w0
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; CHECK: fmlal za.h[w8, 0:1, vgx2], { z0.b, z1.b }, { z2.b, z3.b }
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; CHECK: fmlal za.h[w8, 6:7, vgx2], { z0.b, z1.b }, { z2.b, z3.b }
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; CHECK: ret
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call void @llvm.aarch64.sme.fp8.fmlal.multi.za16.vg2x2(i32 %slice,
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<vscale x 16 x i8> %zn0, <vscale x 16 x i8> %zn1,
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<vscale x 16 x i8> %zm0, <vscale x 16 x i8> %zm1)
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%add = add i32 %slice, 6
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call void @llvm.aarch64.sme.fp8.fmlal.multi.za16.vg2x2(i32 %add,
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<vscale x 16 x i8> %zn0, <vscale x 16 x i8> %zn1,
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<vscale x 16 x i8> %zm0, <vscale x 16 x i8> %zm1)
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ret void
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}
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define void @test_fmlal_multi_vg2x4(i32 %slice, <vscale x 16 x i8> %zn0, <vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zn2, <vscale x 16 x i8> %zn3,
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; CHECK-LABEL: test_fmlal_multi_vg2x4:
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; CHECK: // %bb.0:
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; CHECK: mov w8, w0
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; CHECK: fmlal za.h[w8, 0:1, vgx4], { z0.b - z3.b }, { z4.b - z7.b }
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; CHECK: fmlal za.h[w8, 6:7, vgx4], { z0.b - z3.b }, { z4.b - z7.b }
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; CHECK: ret
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<vscale x 16 x i8> %zm0, <vscale x 16 x i8> %zm1, <vscale x 16 x i8> %zm2, <vscale x 16 x i8> %zm3) {
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call void @llvm.aarch64.sme.fp8.fmlal.multi.za16.vg2x4(i32 %slice,
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<vscale x 16 x i8> %zn0, <vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zn2, <vscale x 16 x i8> %zn3,
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<vscale x 16 x i8> %zm0, <vscale x 16 x i8> %zm1, <vscale x 16 x i8> %zm2, <vscale x 16 x i8> %zm3)
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%add = add i32 %slice, 6
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call void @llvm.aarch64.sme.fp8.fmlal.multi.za16.vg2x4(i32 %add,
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<vscale x 16 x i8> %zn0, <vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zn2, <vscale x 16 x i8> %zn3,
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<vscale x 16 x i8> %zm0, <vscale x 16 x i8> %zm1, <vscale x 16 x i8> %zm2, <vscale x 16 x i8> %zm3)
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ret void
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}
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; FMLALL (multi)
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define void @test_fmlal_multi_vg4x2(i32 %slice, <vscale x 16 x i8> %zn0, <vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zm0, <vscale x 16 x i8> %zm1) {
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; CHECK-LABEL: test_fmlal_multi_vg4x2:
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; CHECK: // %bb.0:
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; CHECK: mov w8, w0
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; CHECK: fmlall za.s[w8, 0:3, vgx2], { z0.b, z1.b }, { z2.b, z3.b }
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; CHECK: fmlall za.s[w8, 4:7, vgx2], { z0.b, z1.b }, { z2.b, z3.b }
|
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; CHECK: ret
|
|
call void @llvm.aarch64.sme.fp8.fmlall.multi.za32.vg4x2(i32 %slice,
|
|
<vscale x 16 x i8> %zn0, <vscale x 16 x i8> %zn1,
|
|
<vscale x 16 x i8> %zm0, <vscale x 16 x i8> %zm1)
|
|
%add = add i32 %slice, 4
|
|
call void @llvm.aarch64.sme.fp8.fmlall.multi.za32.vg4x2(i32 %add,
|
|
<vscale x 16 x i8> %zn0, <vscale x 16 x i8> %zn1,
|
|
<vscale x 16 x i8> %zm0, <vscale x 16 x i8> %zm1)
|
|
ret void
|
|
}
|
|
|
|
define void @test_fmlal_multi_vg4x4(i32 %slice, <vscale x 16 x i8> %zn0, <vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zn2, <vscale x 16 x i8> %zn3,
|
|
; CHECK-LABEL: test_fmlal_multi_vg4x4:
|
|
; CHECK: // %bb.0:
|
|
; CHECK: mov w8, w0
|
|
; CHECK: fmlall za.s[w8, 0:3, vgx4], { z0.b - z3.b }, { z4.b - z7.b }
|
|
; CHECK: fmlall za.s[w8, 4:7, vgx4], { z0.b - z3.b }, { z4.b - z7.b }
|
|
; CHECK: ret
|
|
<vscale x 16 x i8> %zm0, <vscale x 16 x i8> %zm1, <vscale x 16 x i8> %zm2, <vscale x 16 x i8> %zm3) {
|
|
call void @llvm.aarch64.sme.fp8.fmlall.multi.za32.vg4x4(i32 %slice,
|
|
<vscale x 16 x i8> %zn0, <vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zn2, <vscale x 16 x i8> %zn3,
|
|
<vscale x 16 x i8> %zm0, <vscale x 16 x i8> %zm1, <vscale x 16 x i8> %zm2, <vscale x 16 x i8> %zm3)
|
|
%add = add i32 %slice, 4
|
|
call void @llvm.aarch64.sme.fp8.fmlall.multi.za32.vg4x4(i32 %add,
|
|
<vscale x 16 x i8> %zn0, <vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zn2, <vscale x 16 x i8> %zn3,
|
|
<vscale x 16 x i8> %zm0, <vscale x 16 x i8> %zm1, <vscale x 16 x i8> %zm2, <vscale x 16 x i8> %zm3)
|
|
ret void
|
|
}
|