derek.holloway
7502bf64a4
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125 lines
6.3 KiB
LLVM
125 lines
6.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
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; RUN: llc -force-streaming -verify-machineinstrs < %s | FileCheck %s
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target triple = "aarch64-linux"
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define void @add_f16_vg1x2(i32 %slice, <vscale x 8 x half> %zn0, <vscale x 8 x half> %zn1) #0 {
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; CHECK-LABEL: add_f16_vg1x2:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w8, w0
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; CHECK-NEXT: fadd za.h[w8, 0, vgx2], { z0.h, z1.h }
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; CHECK-NEXT: fadd za.h[w8, 7, vgx2], { z0.h, z1.h }
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; CHECK-NEXT: ret
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call void @llvm.aarch64.sme.add.za16.vg1x2.nxv8f16(i32 %slice, <vscale x 8 x half> %zn0, <vscale x 8 x half> %zn1)
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%slice.7 = add i32 %slice, 7
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call void @llvm.aarch64.sme.add.za16.vg1x2.nxv8f16(i32 %slice.7, <vscale x 8 x half> %zn0, <vscale x 8 x half> %zn1)
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ret void
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}
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define void @add_f16_vg1x4(i32 %slice, <vscale x 8 x half> %zn0, <vscale x 8 x half> %zn1,
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; CHECK-LABEL: add_f16_vg1x4:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w8, w0
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; CHECK-NEXT: fadd za.h[w8, 0, vgx4], { z0.h - z3.h }
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; CHECK-NEXT: fadd za.h[w8, 7, vgx4], { z0.h - z3.h }
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; CHECK-NEXT: ret
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<vscale x 8 x half> %zn2, <vscale x 8 x half> %zn3) #1 {
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call void @llvm.aarch64.sme.add.za16.vg1x4.nxv8f16(i32 %slice, <vscale x 8 x half> %zn0, <vscale x 8 x half> %zn1,
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<vscale x 8 x half> %zn2, <vscale x 8 x half> %zn3);
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%slice.7 = add i32 %slice, 7
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call void @llvm.aarch64.sme.add.za16.vg1x4.nxv8f16(i32 %slice.7, <vscale x 8 x half> %zn0, <vscale x 8 x half> %zn1,
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<vscale x 8 x half> %zn2, <vscale x 8 x half> %zn3);
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ret void
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}
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define void @sub_f16_vg1x2(i32 %slice, <vscale x 8 x half> %zn0, <vscale x 8 x half> %zn1) #1 {
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; CHECK-LABEL: sub_f16_vg1x2:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w8, w0
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; CHECK-NEXT: fsub za.h[w8, 0, vgx2], { z0.h, z1.h }
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; CHECK-NEXT: fsub za.h[w8, 7, vgx2], { z0.h, z1.h }
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; CHECK-NEXT: ret
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call void @llvm.aarch64.sme.sub.za16.vg1x2.nxv8f16(i32 %slice, <vscale x 8 x half> %zn0, <vscale x 8 x half> %zn1)
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%slice.7 = add i32 %slice, 7
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call void @llvm.aarch64.sme.sub.za16.vg1x2.nxv8f16(i32 %slice.7, <vscale x 8 x half> %zn0, <vscale x 8 x half> %zn1)
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ret void
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}
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define void @sub_f16_vg1x4(i32 %slice, <vscale x 8 x half> %zn0, <vscale x 8 x half> %zn1,
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; CHECK-LABEL: sub_f16_vg1x4:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w8, w0
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; CHECK-NEXT: fsub za.h[w8, 0, vgx4], { z0.h - z3.h }
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; CHECK-NEXT: fsub za.h[w8, 7, vgx4], { z0.h - z3.h }
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; CHECK-NEXT: ret
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<vscale x 8 x half> %zn2, <vscale x 8 x half> %zn3) #0 {
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call void @llvm.aarch64.sme.sub.za16.vg1x4.nxv8f16(i32 %slice, <vscale x 8 x half> %zn0, <vscale x 8 x half> %zn1,
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<vscale x 8 x half> %zn2, <vscale x 8 x half> %zn3);
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%slice.7 = add i32 %slice, 7
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call void @llvm.aarch64.sme.sub.za16.vg1x4.nxv8f16(i32 %slice.7, <vscale x 8 x half> %zn0, <vscale x 8 x half> %zn1,
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<vscale x 8 x half> %zn2, <vscale x 8 x half> %zn3);
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ret void
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}
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define void @add_bf16_vg1x2(i32 %slice, <vscale x 8 x bfloat> %zn0, <vscale x 8 x bfloat> %zn1) #2 {
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; CHECK-LABEL: add_bf16_vg1x2:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w8, w0
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; CHECK-NEXT: bfadd za.h[w8, 0, vgx2], { z0.h, z1.h }
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; CHECK-NEXT: bfadd za.h[w8, 7, vgx2], { z0.h, z1.h }
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; CHECK-NEXT: ret
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call void @llvm.aarch64.sme.add.za16.vg1x2.nxv8bf16(i32 %slice, <vscale x 8 x bfloat> %zn0, <vscale x 8 x bfloat> %zn1)
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%slice.7 = add i32 %slice, 7
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call void @llvm.aarch64.sme.add.za16.vg1x2.nxv8bf16(i32 %slice.7, <vscale x 8 x bfloat> %zn0, <vscale x 8 x bfloat> %zn1)
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ret void
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}
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define void @add_bf16_vg1x4(i32 %slice, <vscale x 8 x bfloat> %zn0, <vscale x 8 x bfloat> %zn1,
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; CHECK-LABEL: add_bf16_vg1x4:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w8, w0
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; CHECK-NEXT: bfadd za.h[w8, 0, vgx4], { z0.h - z3.h }
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; CHECK-NEXT: bfadd za.h[w8, 7, vgx4], { z0.h - z3.h }
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; CHECK-NEXT: ret
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<vscale x 8 x bfloat> %zn2, <vscale x 8 x bfloat> %zn3) #2 {
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call void @llvm.aarch64.sme.add.za16.vg1x4.nxv8bf16(i32 %slice, <vscale x 8 x bfloat> %zn0, <vscale x 8 x bfloat> %zn1,
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<vscale x 8 x bfloat> %zn2, <vscale x 8 x bfloat> %zn3);
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%slice.7 = add i32 %slice, 7
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call void @llvm.aarch64.sme.add.za16.vg1x4.nxv8bf16(i32 %slice.7, <vscale x 8 x bfloat> %zn0, <vscale x 8 x bfloat> %zn1,
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<vscale x 8 x bfloat> %zn2, <vscale x 8 x bfloat> %zn3);
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ret void
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}
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define void @sub_bf16_vg1x2(i32 %slice, <vscale x 8 x bfloat> %zn0, <vscale x 8 x bfloat> %zn1) #2 {
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; CHECK-LABEL: sub_bf16_vg1x2:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w8, w0
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; CHECK-NEXT: bfsub za.h[w8, 0, vgx2], { z0.h, z1.h }
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; CHECK-NEXT: bfsub za.h[w8, 7, vgx2], { z0.h, z1.h }
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; CHECK-NEXT: ret
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call void @llvm.aarch64.sme.sub.za16.vg1x2.nxv8bf16(i32 %slice, <vscale x 8 x bfloat> %zn0, <vscale x 8 x bfloat> %zn1)
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%slice.7 = add i32 %slice, 7
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call void @llvm.aarch64.sme.sub.za16.vg1x2.nxv8bf16(i32 %slice.7, <vscale x 8 x bfloat> %zn0, <vscale x 8 x bfloat> %zn1)
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ret void
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}
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define void @sub_bf16_vg1x4(i32 %slice, <vscale x 8 x bfloat> %zn0, <vscale x 8 x bfloat> %zn1,
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; CHECK-LABEL: sub_bf16_vg1x4:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w8, w0
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; CHECK-NEXT: bfsub za.h[w8, 0, vgx4], { z0.h - z3.h }
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; CHECK-NEXT: bfsub za.h[w8, 7, vgx4], { z0.h - z3.h }
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; CHECK-NEXT: ret
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<vscale x 8 x bfloat> %zn2, <vscale x 8 x bfloat> %zn3) #2 {
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call void @llvm.aarch64.sme.sub.za16.vg1x4.nxv8bf16(i32 %slice, <vscale x 8 x bfloat> %zn0, <vscale x 8 x bfloat> %zn1,
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<vscale x 8 x bfloat> %zn2, <vscale x 8 x bfloat> %zn3);
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%slice.7 = add i32 %slice, 7
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call void @llvm.aarch64.sme.sub.za16.vg1x4.nxv8bf16(i32 %slice.7, <vscale x 8 x bfloat> %zn0, <vscale x 8 x bfloat> %zn1,
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<vscale x 8 x bfloat> %zn2, <vscale x 8 x bfloat> %zn3);
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ret void
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}
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attributes #0 = { nounwind "target-features"="+sme-f16f16" }
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attributes #1 = { nounwind "target-features"="+sme-f8f16" }
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attributes #2 = { nounwind "target-features"="+sme-b16b16,+bf16" }
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