derek.holloway
7502bf64a4
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236 lines
14 KiB
LLVM
236 lines
14 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme -mattr=+sme2 -mattr=+faminmax -force-streaming -verify-machineinstrs < %s | FileCheck %s
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; FAMAX (Multi, x2)
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define { <vscale x 8 x half>, <vscale x 8 x half> } @multi_vec_max_multi_x2_f16(<vscale x 8 x half> %unused, <vscale x 8 x half> %zdn1, <vscale x 8 x half> %zdn2, <vscale x 8 x half> %zm1, <vscale x 8 x half> %zm2) {
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; CHECK-LABEL: multi_vec_max_multi_x2_f16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov z7.d, z4.d
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; CHECK-NEXT: mov z5.d, z2.d
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; CHECK-NEXT: mov z6.d, z3.d
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; CHECK-NEXT: mov z4.d, z1.d
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; CHECK-NEXT: famax { z4.h, z5.h }, { z4.h, z5.h }, { z6.h, z7.h }
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; CHECK-NEXT: mov z0.d, z4.d
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; CHECK-NEXT: mov z1.d, z5.d
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; CHECK-NEXT: ret
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%res = call { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sme.famax.x2.nxv8f16(<vscale x 8 x half> %zdn1, <vscale x 8 x half> %zdn2, <vscale x 8 x half> %zm1, <vscale x 8 x half> %zm2)
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ret { <vscale x 8 x half>, <vscale x 8 x half> } %res
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}
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define { <vscale x 4 x float>, <vscale x 4 x float> } @multi_vec_max_multi_x2_f32(<vscale x 4 x float> %unused, <vscale x 4 x float> %zdn1, <vscale x 4 x float> %zdn2, <vscale x 4 x float> %zm1, <vscale x 4 x float> %zm2) {
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; CHECK-LABEL: multi_vec_max_multi_x2_f32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov z7.d, z4.d
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; CHECK-NEXT: mov z5.d, z2.d
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; CHECK-NEXT: mov z6.d, z3.d
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; CHECK-NEXT: mov z4.d, z1.d
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; CHECK-NEXT: famax { z4.s, z5.s }, { z4.s, z5.s }, { z6.s, z7.s }
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; CHECK-NEXT: mov z0.d, z4.d
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; CHECK-NEXT: mov z1.d, z5.d
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; CHECK-NEXT: ret
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%res = call { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sme.famax.x2.nxv4f32(<vscale x 4 x float> %zdn1, <vscale x 4 x float> %zdn2, <vscale x 4 x float> %zm1, <vscale x 4 x float> %zm2)
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ret { <vscale x 4 x float>, <vscale x 4 x float> } %res
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}
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define { <vscale x 2 x double>, <vscale x 2 x double> } @multi_vec_max_multi_x2_f64(<vscale x 2 x double> %unused, <vscale x 2 x double> %zdn1, <vscale x 2 x double> %zdn2, <vscale x 2 x double> %zm1, <vscale x 2 x double> %zm2) {
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; CHECK-LABEL: multi_vec_max_multi_x2_f64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov z7.d, z4.d
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; CHECK-NEXT: mov z5.d, z2.d
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; CHECK-NEXT: mov z6.d, z3.d
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; CHECK-NEXT: mov z4.d, z1.d
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; CHECK-NEXT: famax { z4.d, z5.d }, { z4.d, z5.d }, { z6.d, z7.d }
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; CHECK-NEXT: mov z0.d, z4.d
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; CHECK-NEXT: mov z1.d, z5.d
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; CHECK-NEXT: ret
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%res = call { <vscale x 2 x double>, <vscale x 2 x double> } @llvm.aarch64.sme.famax.x2.nxv2f64(<vscale x 2 x double> %zdn1, <vscale x 2 x double> %zdn2, <vscale x 2 x double> %zm1, <vscale x 2 x double> %zm2)
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ret { <vscale x 2 x double>, <vscale x 2 x double> } %res
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}
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; FAMAX (Multi, x4)
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define { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> }@multi_vec_max_multi_x4_f16(<vscale x 8 x half> %unused, <vscale x 8 x half> %zdn1, <vscale x 8 x half> %zdn2, <vscale x 8 x half> %zdn3, <vscale x 8 x half> %zdn4, <vscale x 8 x half> %zm1, <vscale x 8 x half> %zm2, <vscale x 8 x half> %zm3, <vscale x 8 x half> %zm4) {
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; CHECK-LABEL: multi_vec_max_multi_x4_f16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov z26.d, z7.d
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; CHECK-NEXT: mov z25.d, z6.d
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; CHECK-NEXT: ldr z27, [x0]
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; CHECK-NEXT: mov z7.d, z4.d
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; CHECK-NEXT: mov z24.d, z5.d
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; CHECK-NEXT: mov z6.d, z3.d
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; CHECK-NEXT: mov z5.d, z2.d
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; CHECK-NEXT: mov z4.d, z1.d
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; CHECK-NEXT: famax { z4.h - z7.h }, { z4.h - z7.h }, { z24.h - z27.h }
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; CHECK-NEXT: mov z0.d, z4.d
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; CHECK-NEXT: mov z1.d, z5.d
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; CHECK-NEXT: mov z2.d, z6.d
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; CHECK-NEXT: mov z3.d, z7.d
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; CHECK-NEXT: ret
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%res = call { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sme.famax.x4.nxv8f16(<vscale x 8 x half> %zdn1, <vscale x 8 x half> %zdn2, <vscale x 8 x half> %zdn3, <vscale x 8 x half> %zdn4, <vscale x 8 x half> %zm1, <vscale x 8 x half> %zm2, <vscale x 8 x half> %zm3, <vscale x 8 x half> %zm4)
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ret { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %res
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}
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define { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @multi_vec_max_multi_x4_f32(<vscale x 4 x float> %unused, <vscale x 4 x float> %zdn1, <vscale x 4 x float> %zdn2, <vscale x 4 x float> %zdn3, <vscale x 4 x float> %zdn4, <vscale x 4 x float> %zm1, <vscale x 4 x float> %zm2, <vscale x 4 x float> %zm3, <vscale x 4 x float> %zm4) {
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; CHECK-LABEL: multi_vec_max_multi_x4_f32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov z26.d, z7.d
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; CHECK-NEXT: mov z25.d, z6.d
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; CHECK-NEXT: ldr z27, [x0]
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; CHECK-NEXT: mov z7.d, z4.d
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; CHECK-NEXT: mov z24.d, z5.d
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; CHECK-NEXT: mov z6.d, z3.d
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; CHECK-NEXT: mov z5.d, z2.d
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; CHECK-NEXT: mov z4.d, z1.d
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; CHECK-NEXT: famax { z4.s - z7.s }, { z4.s - z7.s }, { z24.s - z27.s }
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; CHECK-NEXT: mov z0.d, z4.d
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; CHECK-NEXT: mov z1.d, z5.d
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; CHECK-NEXT: mov z2.d, z6.d
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; CHECK-NEXT: mov z3.d, z7.d
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; CHECK-NEXT: ret
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%res = call { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sme.famax.x4.nxv4f32(<vscale x 4 x float> %zdn1, <vscale x 4 x float> %zdn2, <vscale x 4 x float> %zdn3, <vscale x 4 x float> %zdn4, <vscale x 4 x float> %zm1, <vscale x 4 x float> %zm2, <vscale x 4 x float> %zm3, <vscale x 4 x float> %zm4)
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ret { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %res
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}
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define { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } @multi_vec_max_multi_x4_f64(<vscale x 2 x double> %unused, <vscale x 2 x double> %zdn1, <vscale x 2 x double> %zdn2, <vscale x 2 x double> %zdn3, <vscale x 2 x double> %zdn4, <vscale x 2 x double> %zm1, <vscale x 2 x double> %zm2, <vscale x 2 x double> %zm3, <vscale x 2 x double> %zm4) {
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; CHECK-LABEL: multi_vec_max_multi_x4_f64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov z26.d, z7.d
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; CHECK-NEXT: mov z25.d, z6.d
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; CHECK-NEXT: ldr z27, [x0]
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; CHECK-NEXT: mov z7.d, z4.d
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; CHECK-NEXT: mov z24.d, z5.d
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; CHECK-NEXT: mov z6.d, z3.d
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; CHECK-NEXT: mov z5.d, z2.d
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; CHECK-NEXT: mov z4.d, z1.d
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; CHECK-NEXT: famax { z4.d - z7.d }, { z4.d - z7.d }, { z24.d - z27.d }
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; CHECK-NEXT: mov z0.d, z4.d
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; CHECK-NEXT: mov z1.d, z5.d
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; CHECK-NEXT: mov z2.d, z6.d
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; CHECK-NEXT: mov z3.d, z7.d
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; CHECK-NEXT: ret
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%res = call { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> }
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@llvm.aarch64.sme.famax.x4.nxv2f64(<vscale x 2 x double> %zdn1, <vscale x 2 x double> %zdn2, <vscale x 2 x double> %zdn3, <vscale x 2 x double> %zdn4,
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<vscale x 2 x double> %zm1, <vscale x 2 x double> %zm2, <vscale x 2 x double> %zm3, <vscale x 2 x double> %zm4)
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ret { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } %res
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}
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; FAMIN (Multi, x2)
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define { <vscale x 8 x half>, <vscale x 8 x half> } @multi_vec_min_multi_x2_f16(<vscale x 8 x half> %unused, <vscale x 8 x half> %zdn1, <vscale x 8 x half> %zdn2, <vscale x 8 x half> %zm1, <vscale x 8 x half> %zm2) {
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; CHECK-LABEL: multi_vec_min_multi_x2_f16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov z7.d, z4.d
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; CHECK-NEXT: mov z5.d, z2.d
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; CHECK-NEXT: mov z6.d, z3.d
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; CHECK-NEXT: mov z4.d, z1.d
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; CHECK-NEXT: famin { z4.h, z5.h }, { z4.h, z5.h }, { z6.h, z7.h }
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; CHECK-NEXT: mov z0.d, z4.d
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; CHECK-NEXT: mov z1.d, z5.d
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; CHECK-NEXT: ret
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%res = call { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sme.famin.x2.nxv8f16(<vscale x 8 x half> %zdn1, <vscale x 8 x half> %zdn2, <vscale x 8 x half> %zm1, <vscale x 8 x half> %zm2)
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ret { <vscale x 8 x half>, <vscale x 8 x half> } %res
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}
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define { <vscale x 4 x float>, <vscale x 4 x float> } @multi_vec_min_multi_x2_f32(<vscale x 4 x float> %unused, <vscale x 4 x float> %zdn1, <vscale x 4 x float> %zdn2, <vscale x 4 x float> %zm1, <vscale x 4 x float> %zm2) {
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; CHECK-LABEL: multi_vec_min_multi_x2_f32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov z7.d, z4.d
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; CHECK-NEXT: mov z5.d, z2.d
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; CHECK-NEXT: mov z6.d, z3.d
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; CHECK-NEXT: mov z4.d, z1.d
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; CHECK-NEXT: famin { z4.s, z5.s }, { z4.s, z5.s }, { z6.s, z7.s }
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; CHECK-NEXT: mov z0.d, z4.d
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; CHECK-NEXT: mov z1.d, z5.d
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; CHECK-NEXT: ret
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%res = call { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sme.famin.x2.nxv4f32(<vscale x 4 x float> %zdn1, <vscale x 4 x float> %zdn2, <vscale x 4 x float> %zm1, <vscale x 4 x float> %zm2)
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ret { <vscale x 4 x float>, <vscale x 4 x float> } %res
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}
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define { <vscale x 2 x double>, <vscale x 2 x double> } @multi_vec_main_multi_x2_f64(<vscale x 2 x double> %unused, <vscale x 2 x double> %zdn1, <vscale x 2 x double> %zdn2, <vscale x 2 x double> %zm1, <vscale x 2 x double> %zm2) {
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; CHECK-LABEL: multi_vec_main_multi_x2_f64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov z7.d, z4.d
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; CHECK-NEXT: mov z5.d, z2.d
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; CHECK-NEXT: mov z6.d, z3.d
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; CHECK-NEXT: mov z4.d, z1.d
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; CHECK-NEXT: famin { z4.d, z5.d }, { z4.d, z5.d }, { z6.d, z7.d }
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; CHECK-NEXT: mov z0.d, z4.d
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; CHECK-NEXT: mov z1.d, z5.d
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; CHECK-NEXT: ret
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%res = call { <vscale x 2 x double>, <vscale x 2 x double> } @llvm.aarch64.sme.famin.x2.nxv2f64(<vscale x 2 x double> %zdn1, <vscale x 2 x double> %zdn2, <vscale x 2 x double> %zm1, <vscale x 2 x double> %zm2)
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ret { <vscale x 2 x double>, <vscale x 2 x double> } %res
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}
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; FAMIN (Multi, x4)
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define { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } @multi_vec_min_multi_x4_f16(<vscale x 8 x half> %unused, <vscale x 8 x half> %zdn1, <vscale x 8 x half> %zdn2, <vscale x 8 x half> %zdn3, <vscale x 8 x half> %zdn4, <vscale x 8 x half> %zm1, <vscale x 8 x half> %zm2, <vscale x 8 x half> %zm3, <vscale x 8 x half> %zm4) {
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; CHECK-LABEL: multi_vec_min_multi_x4_f16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov z26.d, z7.d
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; CHECK-NEXT: mov z25.d, z6.d
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; CHECK-NEXT: ldr z27, [x0]
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; CHECK-NEXT: mov z7.d, z4.d
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; CHECK-NEXT: mov z24.d, z5.d
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; CHECK-NEXT: mov z6.d, z3.d
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; CHECK-NEXT: mov z5.d, z2.d
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; CHECK-NEXT: mov z4.d, z1.d
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; CHECK-NEXT: famin { z4.h - z7.h }, { z4.h - z7.h }, { z24.h - z27.h }
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; CHECK-NEXT: mov z0.d, z4.d
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; CHECK-NEXT: mov z1.d, z5.d
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; CHECK-NEXT: mov z2.d, z6.d
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; CHECK-NEXT: mov z3.d, z7.d
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; CHECK-NEXT: ret
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%res = call { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> }
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@llvm.aarch64.sme.famin.x4.nxv8f16(<vscale x 8 x half> %zdn1, <vscale x 8 x half> %zdn2, <vscale x 8 x half> %zdn3, <vscale x 8 x half> %zdn4,
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<vscale x 8 x half> %zm1, <vscale x 8 x half> %zm2, <vscale x 8 x half> %zm3, <vscale x 8 x half> %zm4)
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ret { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %res
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}
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define { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @multi_vec_min_multi_x4_f32(<vscale x 4 x float> %unused, <vscale x 4 x float> %zdn1, <vscale x 4 x float> %zdn2, <vscale x 4 x float> %zdn3, <vscale x 4 x float> %zdn4, <vscale x 4 x float> %zm1, <vscale x 4 x float> %zm2, <vscale x 4 x float> %zm3, <vscale x 4 x float> %zm4) {
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; CHECK-LABEL: multi_vec_min_multi_x4_f32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov z26.d, z7.d
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; CHECK-NEXT: mov z25.d, z6.d
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; CHECK-NEXT: ldr z27, [x0]
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; CHECK-NEXT: mov z7.d, z4.d
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; CHECK-NEXT: mov z24.d, z5.d
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; CHECK-NEXT: mov z6.d, z3.d
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; CHECK-NEXT: mov z5.d, z2.d
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; CHECK-NEXT: mov z4.d, z1.d
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; CHECK-NEXT: famin { z4.s - z7.s }, { z4.s - z7.s }, { z24.s - z27.s }
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; CHECK-NEXT: mov z0.d, z4.d
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; CHECK-NEXT: mov z1.d, z5.d
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; CHECK-NEXT: mov z2.d, z6.d
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; CHECK-NEXT: mov z3.d, z7.d
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; CHECK-NEXT: ret
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%res = call { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }
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@llvm.aarch64.sme.famin.x4.nxv4f32(<vscale x 4 x float> %zdn1, <vscale x 4 x float> %zdn2, <vscale x 4 x float> %zdn3, <vscale x 4 x float> %zdn4,
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<vscale x 4 x float> %zm1, <vscale x 4 x float> %zm2, <vscale x 4 x float> %zm3, <vscale x 4 x float> %zm4)
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ret { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %res
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}
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define { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } @multi_vec_min_multi_x4_f64(<vscale x 2 x double> %unused, <vscale x 2 x double> %zdn1, <vscale x 2 x double> %zdn2, <vscale x 2 x double> %zdn3, <vscale x 2 x double> %zdn4, <vscale x 2 x double> %zm1, <vscale x 2 x double> %zm2, <vscale x 2 x double> %zm3, <vscale x 2 x double> %zm4) {
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; CHECK-LABEL: multi_vec_min_multi_x4_f64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov z26.d, z7.d
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; CHECK-NEXT: mov z25.d, z6.d
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; CHECK-NEXT: ldr z27, [x0]
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; CHECK-NEXT: mov z7.d, z4.d
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; CHECK-NEXT: mov z24.d, z5.d
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; CHECK-NEXT: mov z6.d, z3.d
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; CHECK-NEXT: mov z5.d, z2.d
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; CHECK-NEXT: mov z4.d, z1.d
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; CHECK-NEXT: famin { z4.d - z7.d }, { z4.d - z7.d }, { z24.d - z27.d }
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; CHECK-NEXT: mov z0.d, z4.d
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; CHECK-NEXT: mov z1.d, z5.d
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; CHECK-NEXT: mov z2.d, z6.d
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; CHECK-NEXT: mov z3.d, z7.d
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; CHECK-NEXT: ret
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%res = call { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> }
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@llvm.aarch64.sme.famin.x4.nxv2f64(<vscale x 2 x double> %zdn1, <vscale x 2 x double> %zdn2, <vscale x 2 x double> %zdn3, <vscale x 2 x double> %zdn4,
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<vscale x 2 x double> %zm1, <vscale x 2 x double> %zm2, <vscale x 2 x double> %zm3, <vscale x 2 x double> %zm4)
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ret { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } %res
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}
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