derek.holloway
7502bf64a4
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172 lines
8.8 KiB
LLVM
172 lines
8.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --filter-out "^[ \t]*//.*$" --version 4
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; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme2,+sme-f8f16,+sme-f8f32 -verify-machineinstrs -force-streaming < %s | FileCheck %s
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target triple = "aarch64-linux"
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define void @test_fdot16_1x2_indexed(i32 %slice.0, <vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zn2, <vscale x 16 x i8> %zm) #0 {
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; CHECK-LABEL: test_fdot16_1x2_indexed:
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; CHECK: mov w8, w0
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; CHECK: fdot za.h[w8, 7, vgx2], { z0.b, z1.b }, z2.b[1]
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; CHECK: ret
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%slice = add i32 %slice.0, 7
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call void @llvm.aarch64.sme.fp8.fdot.lane.za16.vg1x2(i32 %slice,
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<vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zn2,
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<vscale x 16 x i8> %zm, i32 1)
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ret void
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}
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define void @test_fdot16_1x4_indexed(i32 %slice.0, <vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zn2, <vscale x 16 x i8> %zn3, <vscale x 16 x i8> %zn4,
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; CHECK-LABEL: test_fdot16_1x4_indexed:
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; CHECK: mov w8, w0
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; CHECK: fdot za.h[w8, 7, vgx4], { z0.b - z3.b }, z4.b[1]
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; CHECK: ret
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<vscale x 16 x i8> %zm) #0 {
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%slice = add i32 %slice.0, 7
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call void @llvm.aarch64.sme.fp8.fdot.lane.za16.vg1x4(i32 %slice,
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<vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zn2, <vscale x 16 x i8> %zn3, <vscale x 16 x i8> %zn4,
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<vscale x 16 x i8> %zm, i32 1)
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ret void
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}
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define void @test_fdot32_1x2_indexed(i32 %slice.0,
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; CHECK-LABEL: test_fdot32_1x2_indexed:
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; CHECK: mov w8, w0
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; CHECK: fdot za.s[w8, 7, vgx2], { z0.b, z1.b }, z2.b[1]
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; CHECK: ret
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<vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zn2,
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<vscale x 16 x i8> %zm) #0 {
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%slice = add i32 %slice.0, 7
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call void @llvm.aarch64.sme.fp8.fdot.lane.za32.vg1x2(i32 %slice,
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<vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zn2,
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<vscale x 16 x i8> %zm, i32 1)
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ret void
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}
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define void @test_fdot32_1x4_indexed(i32 %slice.0,
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; CHECK-LABEL: test_fdot32_1x4_indexed:
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; CHECK: mov w8, w0
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; CHECK: fdot za.s[w8, 7, vgx4], { z0.b - z3.b }, z4.b[1]
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; CHECK: ret
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<vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zn2, <vscale x 16 x i8> %zn3, <vscale x 16 x i8> %zn4,
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<vscale x 16 x i8> %zm) #0 {
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%slice = add i32 %slice.0, 7
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call void @llvm.aarch64.sme.fp8.fdot.lane.za32.vg1x4(i32 %slice,
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<vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zn2, <vscale x 16 x i8> %zn3, <vscale x 16 x i8> %zn4,
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<vscale x 16 x i8> %zm, i32 1)
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ret void
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}
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define void @test_fdot32_1x2_single(i32 %slice.0,
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; CHECK-LABEL: test_fdot32_1x2_single:
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; CHECK: mov w8, w0
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; CHECK: fdot za.s[w8, 7, vgx2], { z0.b, z1.b }, z2.b
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; CHECK: ret
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<vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zn2,
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<vscale x 16 x i8> %zm) #0 {
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%slice = add i32 %slice.0, 7
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call void @llvm.aarch64.sme.fp8.fdot.single.za32.vg1x2(i32 %slice,
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<vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zn2,
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<vscale x 16 x i8> %zm)
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ret void
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}
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define void @test_fdot32_1x4_single(i32 %slice.0,
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; CHECK-LABEL: test_fdot32_1x4_single:
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; CHECK: mov w8, w0
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; CHECK: fdot za.s[w8, 7, vgx4], { z0.b - z3.b }, z4.b
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; CHECK: ret
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<vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zn2, <vscale x 16 x i8> %zn3, <vscale x 16 x i8> %zn4,
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<vscale x 16 x i8> %zm) #0 {
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%slice = add i32 %slice.0, 7
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call void @llvm.aarch64.sme.fp8.fdot.single.za32.vg1x4(i32 %slice,
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<vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zn2, <vscale x 16 x i8> %zn3, <vscale x 16 x i8> %zn4,
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<vscale x 16 x i8> %zm)
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ret void
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}
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define void @test_fdot32_1x2_multi(i32 %slice.0,
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; CHECK-LABEL: test_fdot32_1x2_multi:
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; CHECK: mov w8, w0
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; CHECK: fdot za.s[w8, 7, vgx2], { z0.b, z1.b }, { z2.b, z3.b }
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; CHECK: ret
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<vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zn2,
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<vscale x 16 x i8> %zm1, <vscale x 16 x i8> %zm2) #0 {
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%slice = add i32 %slice.0, 7
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call void @llvm.aarch64.sme.fp8.fdot.multi.za32.vg1x2(i32 %slice,
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<vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zn2,
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<vscale x 16 x i8> %zm1, <vscale x 16 x i8> %zm2)
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ret void
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}
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define void @test_fdot32_1x4_multi(i32 %slice.0,
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; CHECK-LABEL: test_fdot32_1x4_multi:
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; CHECK: mov w8, w0
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; CHECK: fdot za.s[w8, 7, vgx4], { z0.b - z3.b }, { z4.b - z7.b }
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; CHECK: ret
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<vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zn2, <vscale x 16 x i8> %zn3, <vscale x 16 x i8> %zn4,
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<vscale x 16 x i8> %zm1, <vscale x 16 x i8> %zm2, <vscale x 16 x i8> %zm3, <vscale x 16 x i8> %zm4) #0 {
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%slice = add i32 %slice.0, 7
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call void @llvm.aarch64.sme.fp8.fdot.multi.za32.vg1x4(i32 %slice,
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<vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zn2, <vscale x 16 x i8> %zn3, <vscale x 16 x i8> %zn4,
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<vscale x 16 x i8> %zm1, <vscale x 16 x i8> %zm2, <vscale x 16 x i8> %zm3, <vscale x 16 x i8> %zm4)
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ret void
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}
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define void @test_fdot16_1x2_single(i32 %slice.0,
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; CHECK-LABEL: test_fdot16_1x2_single:
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; CHECK: mov w8, w0
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; CHECK: fdot za.h[w8, 7, vgx2], { z0.b, z1.b }, z2.b
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; CHECK: ret
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<vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zn2,
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<vscale x 16 x i8> %zm) #0 {
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%slice = add i32 %slice.0, 7
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call void @llvm.aarch64.sme.fp8.fdot.single.za16.vg1x2(i32 %slice,
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<vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zn2,
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<vscale x 16 x i8> %zm)
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ret void
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}
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define void @test_fdot16_1x4_single(i32 %slice.0,
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; CHECK-LABEL: test_fdot16_1x4_single:
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; CHECK: mov w8, w0
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; CHECK: fdot za.h[w8, 7, vgx4], { z0.b - z3.b }, z4.b
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; CHECK: ret
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<vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zn2, <vscale x 16 x i8> %zn3, <vscale x 16 x i8> %zn4,
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<vscale x 16 x i8> %zm) #0 {
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%slice = add i32 %slice.0, 7
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call void @llvm.aarch64.sme.fp8.fdot.single.za16.vg1x4(i32 %slice,
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<vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zn2, <vscale x 16 x i8> %zn3, <vscale x 16 x i8> %zn4,
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<vscale x 16 x i8> %zm)
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ret void
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}
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define void @test_fdot16_1x2_multi(i32 %slice.0,
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; CHECK-LABEL: test_fdot16_1x2_multi:
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; CHECK: mov w8, w0
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; CHECK: fdot za.h[w8, 7, vgx2], { z0.b, z1.b }, { z2.b, z3.b }
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; CHECK: ret
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<vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zn2,
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<vscale x 16 x i8> %zm1, <vscale x 16 x i8> %zm2) #0 {
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%slice = add i32 %slice.0, 7
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call void @llvm.aarch64.sme.fp8.fdot.multi.za16.vg1x2(i32 %slice,
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<vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zn2,
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<vscale x 16 x i8> %zm1, <vscale x 16 x i8> %zm2)
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ret void
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}
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define void @test_fdot16_1x4_multi(i32 %slice.0,
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; CHECK-LABEL: test_fdot16_1x4_multi:
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; CHECK: mov w8, w0
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; CHECK: fdot za.h[w8, 7, vgx4], { z0.b - z3.b }, { z4.b - z7.b }
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; CHECK: ret
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<vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zn2, <vscale x 16 x i8> %zn3, <vscale x 16 x i8> %zn4,
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<vscale x 16 x i8> %zm1, <vscale x 16 x i8> %zm2, <vscale x 16 x i8> %zm3, <vscale x 16 x i8> %zm4) #0 {
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%slice = add i32 %slice.0, 7
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call void @llvm.aarch64.sme.fp8.fdot.multi.za16.vg1x4(i32 %slice,
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<vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zn2, <vscale x 16 x i8> %zn3, <vscale x 16 x i8> %zn4,
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<vscale x 16 x i8> %zm1, <vscale x 16 x i8> %zm2, <vscale x 16 x i8> %zm3, <vscale x 16 x i8> %zm4)
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ret void
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}
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attributes #0 = { "target-features" = "+sme,+sme-f8f32,+sme-f8f16" }
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