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91 lines
3.7 KiB
LLVM
91 lines
3.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc -force-streaming -verify-machineinstrs < %s | FileCheck %s
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target triple = "aarch64-linux"
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define void @mop4a_za16_fp8_1x1(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
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; CHECK-LABEL: mop4a_za16_fp8_1x1:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov z24.d, z1.d
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; CHECK-NEXT: fmop4a za0.h, z0.b, z24.b
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; CHECK-NEXT: ret
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call void @llvm.aarch64.sme.fp8.fmop4a.za16.1x1(i32 0, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm)
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ret void
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}
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define void @mop4a_za16_fp8_1x2(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm1, <vscale x 16 x i8> %zm2) #0 {
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; CHECK-LABEL: mop4a_za16_fp8_1x2:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov z25.d, z2.d
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; CHECK-NEXT: mov z24.d, z1.d
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; CHECK-NEXT: fmop4a za0.h, z0.b, { z24.b, z25.b }
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; CHECK-NEXT: ret
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call void @llvm.aarch64.sme.fp8.fmop4a.za16.1x2(i32 0, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm1, <vscale x 16 x i8> %zm2)
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ret void
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}
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define void @mop4a_za16_fp8_2x1(<vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zn2, <vscale x 16 x i8> %zm) #0 {
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; CHECK-LABEL: mop4a_za16_fp8_2x1:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov z24.d, z2.d
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; CHECK-NEXT: fmop4a za0.h, { z0.b, z1.b }, z24.b
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; CHECK-NEXT: ret
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call void @llvm.aarch64.sme.fp8.fmop4a.za16.2x1(i32 0, <vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zn2, <vscale x 16 x i8> %zm)
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ret void
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}
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define void @mop4a_za16_fp8_2x2(<vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zn2, <vscale x 16 x i8> %zm1, <vscale x 16 x i8> %zm2) #0 {
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; CHECK-LABEL: mop4a_za16_fp8_2x2:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov z25.d, z3.d
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; CHECK-NEXT: mov z24.d, z2.d
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; CHECK-NEXT: fmop4a za0.h, { z0.b, z1.b }, { z24.b, z25.b }
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; CHECK-NEXT: ret
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call void @llvm.aarch64.sme.fp8.fmop4a.za16.2x2(i32 0, <vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zn2, <vscale x 16 x i8> %zm1, <vscale x 16 x i8> %zm2)
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ret void
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}
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define void @mop4a_za32_fp8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {
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; CHECK-LABEL: mop4a_za32_fp8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov z24.d, z1.d
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; CHECK-NEXT: fmop4a za0.s, z0.b, z24.b
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; CHECK-NEXT: ret
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call void @llvm.aarch64.sme.fp8.fmop4a.za32.1x1(i32 0, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm)
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ret void
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}
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define void @mop4a_za32_fp8_1x2(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm1, <vscale x 16 x i8> %zm2) #0 {
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; CHECK-LABEL: mop4a_za32_fp8_1x2:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov z25.d, z2.d
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; CHECK-NEXT: mov z24.d, z1.d
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; CHECK-NEXT: fmop4a za0.s, z0.b, { z24.b, z25.b }
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; CHECK-NEXT: ret
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call void @llvm.aarch64.sme.fp8.fmop4a.za32.1x2(i32 0, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm1, <vscale x 16 x i8> %zm2)
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ret void
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}
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define void @mop4a_za32_fp8_2x1(<vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zn2, <vscale x 16 x i8> %zm) #0 {
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; CHECK-LABEL: mop4a_za32_fp8_2x1:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov z24.d, z2.d
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; CHECK-NEXT: fmop4a za0.s, { z0.b, z1.b }, z24.b
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; CHECK-NEXT: ret
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call void @llvm.aarch64.sme.fp8.fmop4a.za32.2x1(i32 0, <vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zn2, <vscale x 16 x i8> %zm)
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ret void
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}
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define void @mop4a_za32_fp8_2x2(<vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zn2, <vscale x 16 x i8> %zm1, <vscale x 16 x i8> %zm2) #0 {
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; CHECK-LABEL: mop4a_za32_fp8_2x2:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov z25.d, z3.d
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; CHECK-NEXT: mov z24.d, z2.d
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; CHECK-NEXT: fmop4a za0.s, { z0.b, z1.b }, { z24.b, z25.b }
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; CHECK-NEXT: ret
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call void @llvm.aarch64.sme.fp8.fmop4a.za32.2x2(i32 0, <vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zn2, <vscale x 16 x i8> %zm1, <vscale x 16 x i8> %zm2)
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ret void
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}
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attributes #0 = {nounwind "target-features" = "+sme-f8f16,+sme-f8f32,+sme2p1,+sme-mop4" }
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