derek.holloway
7502bf64a4
CodeQL / Analyze (actions) (push) Canceled after 0s
CodeQL / Analyze (python) (push) Canceled after 0s
pre-commit / pre-commit (push) Canceled after 0s
Multi-Arch CI / setup (push) Canceled after 0s
Publish build_manylinux_x86_64 images / publish_build_manylinux_x86_64 (push) Canceled after 0s
Setup (Multi-Arch) / setup (push) Canceled after 0s
Multi-Arch CI / Linux::${{ fromJSON(needs.setup.outputs.linux_build_config || '{}').build_variant_label || 'skip' }} (push) Canceled after 0s
Publish TheRock Docker image / build-and-push-image (push) Canceled after 0s
Publish no_rocm_image_ubi10 image / publish_no_rocm_image_ubi10 (push) Canceled after 0s
Multi-Arch CI / Windows::${{ fromJSON(needs.setup.outputs.windows_build_config || '{}').build_variant_label || 'skip' }} (push) Canceled after 0s
Publish TheRock Docker image / build-and-push-image (push) Canceled after 0s
Multi-Arch CI / Manifest Diff (push) Canceled after 0s
TheRock Manifest Diff Report / Generate Manifest Diff Report (push) Canceled after 0s
Multi-Arch CI / CI Summary (push) Canceled after 0s
Publish no_rocm_image_ubuntu24_04 images / publish_no_rocm_image_ubuntu24_04 (push) Canceled after 0s
Publish no_rocm_image_ubuntu24_04_ocl_rt images / publish_no_rocm_image_ubuntu24_04_ocl_rt (push) Canceled after 0s
Publish TheRock Docker image / build-and-push-image (push) Canceled after 0s
Publish TheRock Docker image / build-and-push-image (push) Canceled after 0s
Publish no_rocm_image_ubuntu24_04 images / publish_no_rocm_image_ubuntu24_04_rocgdb (push) Canceled after 0s
Publish no_rocm_image_ubuntu24_04_rocgdb images / publish_no_rocm_image_ubuntu24_04_rocgdb (push) Canceled after 0s
Publish no_rocm_image_ubuntu24_04 images / publish_no_rocm_image_ubuntu24_04_ocl_rt (push) Canceled after 0s
Publish TheRock Docker image / build-and-push-image (push) Canceled after 0s
Unit Tests / Unit Tests :: ubuntu-24.04 (push) Canceled after 0s
Unit Tests / Unit Tests :: windows-2022 (push) Canceled after 0s
Publish no_rocm_image_ubuntu24_04 images / publish_no_rocm_image_ubuntu24_04_media (push) Canceled after 0s
Unit Tests / Unit Tests Summary (push) Canceled after 0s
Publish no_rocm_image_ubuntu24_04 images / publish_no_rocm_image_ubuntu24_04_openmpi (push) Canceled after 0s
221 lines
13 KiB
LLVM
221 lines
13 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
|
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme2 -force-streaming -enable-subreg-liveness -verify-machineinstrs < %s | FileCheck %s
|
|
|
|
;
|
|
; SQCVT
|
|
;
|
|
|
|
; x2
|
|
define <vscale x 8 x i16 > @multi_vector_qcvt_x2_s16_s32(<vscale x 4 x i32> %unused, <vscale x 4 x i32> %zn1, <vscale x 4 x i32> %zn2) {
|
|
; CHECK-LABEL: multi_vector_qcvt_x2_s16_s32:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: mov z3.d, z2.d
|
|
; CHECK-NEXT: mov z2.d, z1.d
|
|
; CHECK-NEXT: sqcvt z0.h, { z2.s, z3.s }
|
|
; CHECK-NEXT: ret
|
|
%res = call <vscale x 8 x i16> @llvm.aarch64.sve.sqcvt.x2.nxv4i32(<vscale x 4 x i32> %zn1, <vscale x 4 x i32> %zn2)
|
|
ret <vscale x 8 x i16> %res
|
|
}
|
|
|
|
; x4
|
|
define <vscale x 16 x i8 > @multi_vector_qcvt_x4_s8_s32(<vscale x 4 x i32> %unused, <vscale x 4 x i32> %zn1, <vscale x 4 x i32> %zn2, <vscale x 4 x i32> %zn3, <vscale x 4 x i32> %zn4) {
|
|
; CHECK-LABEL: multi_vector_qcvt_x4_s8_s32:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: mov z7.d, z4.d
|
|
; CHECK-NEXT: mov z6.d, z3.d
|
|
; CHECK-NEXT: mov z5.d, z2.d
|
|
; CHECK-NEXT: mov z4.d, z1.d
|
|
; CHECK-NEXT: sqcvt z0.b, { z4.s - z7.s }
|
|
; CHECK-NEXT: ret
|
|
%res = call <vscale x 16 x i8> @llvm.aarch64.sve.sqcvt.x4.nxv4i32(<vscale x 4 x i32> %zn1, <vscale x 4 x i32> %zn2, <vscale x 4 x i32> %zn3, <vscale x 4 x i32> %zn4)
|
|
ret <vscale x 16 x i8> %res
|
|
}
|
|
|
|
define <vscale x 8 x i16> @multi_vector_qcvt_x4_s16_s64(<vscale x 2 x i64> %unused, <vscale x 2 x i64> %zn1, <vscale x 2 x i64> %zn2, <vscale x 2 x i64> %zn3, <vscale x 2 x i64> %zn4) {
|
|
; CHECK-LABEL: multi_vector_qcvt_x4_s16_s64:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: mov z7.d, z4.d
|
|
; CHECK-NEXT: mov z6.d, z3.d
|
|
; CHECK-NEXT: mov z5.d, z2.d
|
|
; CHECK-NEXT: mov z4.d, z1.d
|
|
; CHECK-NEXT: sqcvt z0.h, { z4.d - z7.d }
|
|
; CHECK-NEXT: ret
|
|
%res = call <vscale x 8 x i16> @llvm.aarch64.sve.sqcvt.x4.nxv2i64(<vscale x 2 x i64> %zn1, <vscale x 2 x i64> %zn2, <vscale x 2 x i64> %zn3, <vscale x 2 x i64> %zn4)
|
|
ret <vscale x 8 x i16> %res
|
|
}
|
|
|
|
define { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @multi_vector_qcvt_x4_s16_s64_tuple(i64 %stride, ptr %ptr) {
|
|
; CHECK-LABEL: multi_vector_qcvt_x4_s16_s64_tuple:
|
|
; CHECK: // %bb.0: // %entry
|
|
; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill
|
|
; CHECK-NEXT: addvl sp, sp, #-9
|
|
; CHECK-NEXT: str p8, [sp, #7, mul vl] // 2-byte Spill
|
|
; CHECK-NEXT: str z23, [sp, #1, mul vl] // 16-byte Folded Spill
|
|
; CHECK-NEXT: str z22, [sp, #2, mul vl] // 16-byte Folded Spill
|
|
; CHECK-NEXT: str z21, [sp, #3, mul vl] // 16-byte Folded Spill
|
|
; CHECK-NEXT: str z20, [sp, #4, mul vl] // 16-byte Folded Spill
|
|
; CHECK-NEXT: str z19, [sp, #5, mul vl] // 16-byte Folded Spill
|
|
; CHECK-NEXT: str z18, [sp, #6, mul vl] // 16-byte Folded Spill
|
|
; CHECK-NEXT: str z17, [sp, #7, mul vl] // 16-byte Folded Spill
|
|
; CHECK-NEXT: str z16, [sp, #8, mul vl] // 16-byte Folded Spill
|
|
; CHECK-NEXT: .cfi_escape 0x0f, 0x0a, 0x8f, 0x10, 0x92, 0x2e, 0x00, 0x11, 0xc8, 0x00, 0x1e, 0x22 // sp + 16 + 72 * VG
|
|
; CHECK-NEXT: .cfi_offset w29, -16
|
|
; CHECK-NEXT: lsl x8, x0, #1
|
|
; CHECK-NEXT: add x9, x1, x0
|
|
; CHECK-NEXT: ptrue pn8.b
|
|
; CHECK-NEXT: ld1d { z16.d, z20.d, z24.d, z28.d }, pn8/z, [x1]
|
|
; CHECK-NEXT: ld1d { z17.d, z21.d, z25.d, z29.d }, pn8/z, [x9]
|
|
; CHECK-NEXT: add x10, x1, x8
|
|
; CHECK-NEXT: add x8, x9, x8
|
|
; CHECK-NEXT: ld1d { z18.d, z22.d, z26.d, z30.d }, pn8/z, [x10]
|
|
; CHECK-NEXT: ld1d { z19.d, z23.d, z27.d, z31.d }, pn8/z, [x8]
|
|
; CHECK-NEXT: sqcvt z0.h, { z16.d - z19.d }
|
|
; CHECK-NEXT: sqcvt z1.h, { z20.d - z23.d }
|
|
; CHECK-NEXT: sqcvt z2.h, { z24.d - z27.d }
|
|
; CHECK-NEXT: sqcvt z3.h, { z28.d - z31.d }
|
|
; CHECK-NEXT: ldr z23, [sp, #1, mul vl] // 16-byte Folded Reload
|
|
; CHECK-NEXT: ldr z22, [sp, #2, mul vl] // 16-byte Folded Reload
|
|
; CHECK-NEXT: ldr z21, [sp, #3, mul vl] // 16-byte Folded Reload
|
|
; CHECK-NEXT: ldr z20, [sp, #4, mul vl] // 16-byte Folded Reload
|
|
; CHECK-NEXT: ldr z19, [sp, #5, mul vl] // 16-byte Folded Reload
|
|
; CHECK-NEXT: ldr z18, [sp, #6, mul vl] // 16-byte Folded Reload
|
|
; CHECK-NEXT: ldr z17, [sp, #7, mul vl] // 16-byte Folded Reload
|
|
; CHECK-NEXT: ldr z16, [sp, #8, mul vl] // 16-byte Folded Reload
|
|
; CHECK-NEXT: ldr p8, [sp, #7, mul vl] // 2-byte Reload
|
|
; CHECK-NEXT: addvl sp, sp, #9
|
|
; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload
|
|
; CHECK-NEXT: ret
|
|
entry:
|
|
%0 = tail call target("aarch64.svcount") @llvm.aarch64.sve.ptrue.c8()
|
|
%1 = tail call { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.ld1.pn.x4.nxv2i64(target("aarch64.svcount") %0, ptr %ptr)
|
|
%2 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %1, 0
|
|
%3 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %1, 1
|
|
%4 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %1, 2
|
|
%5 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %1, 3
|
|
%arrayidx2 = getelementptr inbounds i8, ptr %ptr, i64 %stride
|
|
%6 = tail call { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.ld1.pn.x4.nxv2i64(target("aarch64.svcount") %0, ptr %arrayidx2)
|
|
%7 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %6, 0
|
|
%8 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %6, 1
|
|
%9 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %6, 2
|
|
%10 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %6, 3
|
|
%mul3 = shl i64 %stride, 1
|
|
%arrayidx4 = getelementptr inbounds i8, ptr %ptr, i64 %mul3
|
|
%11 = tail call { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.ld1.pn.x4.nxv2i64(target("aarch64.svcount") %0, ptr %arrayidx4)
|
|
%12 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %11, 0
|
|
%13 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %11, 1
|
|
%14 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %11, 2
|
|
%15 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %11, 3
|
|
%mul5 = mul i64 %stride, 3
|
|
%arrayidx6 = getelementptr inbounds i8, ptr %ptr, i64 %mul5
|
|
%16 = tail call { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.ld1.pn.x4.nxv2i64(target("aarch64.svcount") %0, ptr %arrayidx6)
|
|
%17 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %16, 0
|
|
%18 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %16, 1
|
|
%19 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %16, 2
|
|
%20 = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %16, 3
|
|
%res1 = call <vscale x 8 x i16> @llvm.aarch64.sve.sqcvt.x4.nxv2i64(<vscale x 2 x i64> %2, <vscale x 2 x i64> %7, <vscale x 2 x i64> %12, <vscale x 2 x i64> %17)
|
|
%res2 = call <vscale x 8 x i16> @llvm.aarch64.sve.sqcvt.x4.nxv2i64(<vscale x 2 x i64> %3, <vscale x 2 x i64> %8, <vscale x 2 x i64> %13, <vscale x 2 x i64> %18)
|
|
%res3 = call <vscale x 8 x i16> @llvm.aarch64.sve.sqcvt.x4.nxv2i64(<vscale x 2 x i64> %4, <vscale x 2 x i64> %9, <vscale x 2 x i64> %14, <vscale x 2 x i64> %19)
|
|
%res4 = call <vscale x 8 x i16> @llvm.aarch64.sve.sqcvt.x4.nxv2i64(<vscale x 2 x i64> %5, <vscale x 2 x i64> %10, <vscale x 2 x i64> %15, <vscale x 2 x i64> %20)
|
|
%ins1 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } poison, <vscale x 8 x i16> %res1, 0
|
|
%ins2 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %ins1, <vscale x 8 x i16> %res2, 1
|
|
%ins3 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %ins2, <vscale x 8 x i16> %res3, 2
|
|
%ins4 = insertvalue { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %ins3, <vscale x 8 x i16> %res4, 3
|
|
ret { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %ins4
|
|
}
|
|
|
|
;
|
|
; UQCVT
|
|
;
|
|
|
|
; x2
|
|
define <vscale x 8 x i16> @multi_vector_qcvt_x2_u16_u32(<vscale x 4 x i32> %unused, <vscale x 4 x i32> %zn0, <vscale x 4 x i32> %zn1) {
|
|
; CHECK-LABEL: multi_vector_qcvt_x2_u16_u32:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: mov z3.d, z2.d
|
|
; CHECK-NEXT: mov z2.d, z1.d
|
|
; CHECK-NEXT: uqcvt z0.h, { z2.s, z3.s }
|
|
; CHECK-NEXT: ret
|
|
%res = call <vscale x 8 x i16> @llvm.aarch64.sve.uqcvt.x2.nxv4i32(<vscale x 4 x i32> %zn0, <vscale x 4 x i32> %zn1)
|
|
ret<vscale x 8 x i16> %res
|
|
}
|
|
|
|
; x4
|
|
define <vscale x 16 x i8> @multi_vector_qcvt_x4_u8_u32(<vscale x 4 x i32> %unused, <vscale x 4 x i32> %zn1, <vscale x 4 x i32> %zn2, <vscale x 4 x i32> %zn3, <vscale x 4 x i32> %zn4) {
|
|
; CHECK-LABEL: multi_vector_qcvt_x4_u8_u32:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: mov z7.d, z4.d
|
|
; CHECK-NEXT: mov z6.d, z3.d
|
|
; CHECK-NEXT: mov z5.d, z2.d
|
|
; CHECK-NEXT: mov z4.d, z1.d
|
|
; CHECK-NEXT: uqcvt z0.b, { z4.s - z7.s }
|
|
; CHECK-NEXT: ret
|
|
%res = call <vscale x 16 x i8> @llvm.aarch64.sve.uqcvt.x4.nxv4i32(<vscale x 4 x i32> %zn1, <vscale x 4 x i32> %zn2, <vscale x 4 x i32> %zn3, <vscale x 4 x i32> %zn4)
|
|
ret <vscale x 16 x i8> %res
|
|
}
|
|
|
|
define <vscale x 8 x i16> @multi_vector_qcvt_x4_u16_u64(<vscale x 2 x i64> %unused, <vscale x 2 x i64> %zn1, <vscale x 2 x i64> %zn2, <vscale x 2 x i64> %zn3, <vscale x 2 x i64> %zn4) {
|
|
; CHECK-LABEL: multi_vector_qcvt_x4_u16_u64:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: mov z7.d, z4.d
|
|
; CHECK-NEXT: mov z6.d, z3.d
|
|
; CHECK-NEXT: mov z5.d, z2.d
|
|
; CHECK-NEXT: mov z4.d, z1.d
|
|
; CHECK-NEXT: uqcvt z0.h, { z4.d - z7.d }
|
|
; CHECK-NEXT: ret
|
|
%res = call <vscale x 8 x i16> @llvm.aarch64.sve.uqcvt.x4.nxv2i64(<vscale x 2 x i64> %zn1, <vscale x 2 x i64> %zn2, <vscale x 2 x i64> %zn3, <vscale x 2 x i64> %zn4)
|
|
ret <vscale x 8 x i16> %res
|
|
}
|
|
|
|
;
|
|
; SQCVTU
|
|
;
|
|
|
|
; x2
|
|
define <vscale x 8 x i16 > @multi_vector_qcvt_x2_s16_u32(<vscale x 4 x i32> %unused, <vscale x 4 x i32> %zn1, <vscale x 4 x i32> %zn2) {
|
|
; CHECK-LABEL: multi_vector_qcvt_x2_s16_u32:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: mov z3.d, z2.d
|
|
; CHECK-NEXT: mov z2.d, z1.d
|
|
; CHECK-NEXT: sqcvtu z0.h, { z2.s, z3.s }
|
|
; CHECK-NEXT: ret
|
|
%res = call <vscale x 8 x i16> @llvm.aarch64.sve.sqcvtu.x2.nxv4i32(<vscale x 4 x i32> %zn1, <vscale x 4 x i32> %zn2)
|
|
ret <vscale x 8 x i16> %res
|
|
}
|
|
|
|
; x4
|
|
define <vscale x 16 x i8> @multi_vector_qcvt_x4_u8_s32(<vscale x 4 x i32> %unused, <vscale x 4 x i32> %zn1, <vscale x 4 x i32> %zn2, <vscale x 4 x i32> %zn3, <vscale x 4 x i32> %zn4) {
|
|
; CHECK-LABEL: multi_vector_qcvt_x4_u8_s32:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: mov z7.d, z4.d
|
|
; CHECK-NEXT: mov z6.d, z3.d
|
|
; CHECK-NEXT: mov z5.d, z2.d
|
|
; CHECK-NEXT: mov z4.d, z1.d
|
|
; CHECK-NEXT: sqcvtu z0.b, { z4.s - z7.s }
|
|
; CHECK-NEXT: ret
|
|
%res = call <vscale x 16 x i8> @llvm.aarch64.sve.sqcvtu.x4.nxv4i32(<vscale x 4 x i32> %zn1, <vscale x 4 x i32> %zn2, <vscale x 4 x i32> %zn3, <vscale x 4 x i32> %zn4)
|
|
ret <vscale x 16 x i8> %res
|
|
}
|
|
|
|
define <vscale x 8 x i16> @multi_vector_qcvt_x4_u16_s64(<vscale x 2 x i64> %unused, <vscale x 2 x i64> %zn1, <vscale x 2 x i64> %zn2, <vscale x 2 x i64> %zn3, <vscale x 2 x i64> %zn4) {
|
|
; CHECK-LABEL: multi_vector_qcvt_x4_u16_s64:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: mov z7.d, z4.d
|
|
; CHECK-NEXT: mov z6.d, z3.d
|
|
; CHECK-NEXT: mov z5.d, z2.d
|
|
; CHECK-NEXT: mov z4.d, z1.d
|
|
; CHECK-NEXT: sqcvtu z0.h, { z4.d - z7.d }
|
|
; CHECK-NEXT: ret
|
|
%res = call <vscale x 8 x i16> @llvm.aarch64.sve.sqcvtu.x4.nxv2i64(<vscale x 2 x i64> %zn1, <vscale x 2 x i64> %zn2, <vscale x 2 x i64> %zn3, <vscale x 2 x i64> %zn4)
|
|
ret <vscale x 8 x i16> %res
|
|
}
|
|
|
|
declare <vscale x 8 x i16> @llvm.aarch64.sve.sqcvt.x2.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>)
|
|
declare <vscale x 8 x i16> @llvm.aarch64.sve.uqcvt.x2.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>)
|
|
declare <vscale x 8 x i16> @llvm.aarch64.sve.sqcvtu.x2.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>)
|
|
declare <vscale x 16 x i8> @llvm.aarch64.sve.sqcvt.x4.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>)
|
|
declare <vscale x 8 x i16> @llvm.aarch64.sve.sqcvt.x4.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>)
|
|
declare <vscale x 16 x i8> @llvm.aarch64.sve.uqcvt.x4.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>)
|
|
declare <vscale x 8 x i16> @llvm.aarch64.sve.uqcvt.x4.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>)
|
|
declare <vscale x 16 x i8> @llvm.aarch64.sve.sqcvtu.x4.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>)
|
|
declare <vscale x 8 x i16> @llvm.aarch64.sve.sqcvtu.x4.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>)
|