derek.holloway
7502bf64a4
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34 lines
1.3 KiB
LLVM
34 lines
1.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
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; RUN: llc -force-streaming < %s | FileCheck %s
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target triple = "aarch64"
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define <vscale x 2 x i64> @test_tileslice_no_add(i32 %idx) #0 {
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; CHECK-LABEL: test_tileslice_no_add:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: mov w8, w0
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; CHECK-NEXT: mov { z0.d, z1.d }, za.d[w8, 0, vgx2]
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; CHECK-NEXT: ret
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entry:
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%read = call { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sme.read.vg1x2.nxv2i64(i32 %idx)
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%read.ext = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %read, 0
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ret <vscale x 2 x i64> %read.ext
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}
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define <vscale x 2 x i64> @test_tileslice_add_nonconstant(i32 %idx1, i32 %idx2) #0 {
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; CHECK-LABEL: test_tileslice_add_nonconstant:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: add w8, w0, w1
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; CHECK-NEXT: mov { z0.d, z1.d }, za.d[w8, 0, vgx2]
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; CHECK-NEXT: ret
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entry:
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%add = add i32 %idx1, %idx2
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%read = call { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sme.read.vg1x2.nxv2i64(i32 %add)
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%read.ext = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %read, 0
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ret <vscale x 2 x i64> %read.ext
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}
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declare { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sme.read.vg1x2.nxv2i64(i32)
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attributes #0 = { nounwind "target-features"="+sme2" }
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