derek.holloway
7502bf64a4
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283 lines
9.0 KiB
LLVM
283 lines
9.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=aarch64-linux-gnu -global-isel=0 | FileCheck %s --check-prefixes=CHECK,CHECK-SD
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; RUN: llc < %s -mtriple=aarch64-linux-gnu -global-isel | FileCheck %s --check-prefixes=CHECK,CHECK-GI
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define i32 @func(i32 %x, i32 %y) nounwind {
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; CHECK-SD-LABEL: func:
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; CHECK-SD: // %bb.0:
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; CHECK-SD-NEXT: smull x8, w0, w1
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; CHECK-SD-NEXT: lsr x9, x8, #32
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; CHECK-SD-NEXT: extr w0, w9, w8, #2
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: func:
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; CHECK-GI: // %bb.0:
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; CHECK-GI-NEXT: smull x8, w0, w1
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; CHECK-GI-NEXT: asr x0, x8, #2
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; CHECK-GI-NEXT: // kill: def $w0 killed $w0 killed $x0
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; CHECK-GI-NEXT: ret
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%tmp = call i32 @llvm.smul.fix.i32(i32 %x, i32 %y, i32 2)
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ret i32 %tmp
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}
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define i64 @func2(i64 %x, i64 %y) {
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; CHECK-SD-LABEL: func2:
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; CHECK-SD: // %bb.0:
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; CHECK-SD-NEXT: mul x8, x0, x1
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; CHECK-SD-NEXT: smulh x9, x0, x1
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; CHECK-SD-NEXT: extr x0, x9, x8, #2
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: func2:
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; CHECK-GI: // %bb.0:
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; CHECK-GI-NEXT: umulh x8, x0, x1
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; CHECK-GI-NEXT: asr x9, x1, #63
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; CHECK-GI-NEXT: mul x10, x0, x1
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; CHECK-GI-NEXT: madd x8, x0, x9, x8
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; CHECK-GI-NEXT: asr x9, x0, #63
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; CHECK-GI-NEXT: madd x8, x9, x1, x8
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; CHECK-GI-NEXT: extr x0, x8, x10, #2
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; CHECK-GI-NEXT: ret
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%tmp = call i64 @llvm.smul.fix.i64(i64 %x, i64 %y, i32 2)
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ret i64 %tmp
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}
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define i4 @func3(i4 %x, i4 %y) nounwind {
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; CHECK-SD-LABEL: func3:
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; CHECK-SD: // %bb.0:
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; CHECK-SD-NEXT: sbfx w8, w1, #0, #4
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; CHECK-SD-NEXT: sbfx w9, w0, #0, #4
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; CHECK-SD-NEXT: smull x8, w9, w8
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; CHECK-SD-NEXT: lsr x9, x8, #32
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; CHECK-SD-NEXT: extr w0, w9, w8, #2
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: func3:
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; CHECK-GI: // %bb.0:
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; CHECK-GI-NEXT: sbfx w8, w0, #0, #4
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; CHECK-GI-NEXT: sbfx w9, w1, #0, #4
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; CHECK-GI-NEXT: mul w8, w8, w9
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; CHECK-GI-NEXT: sbfx w0, w8, #2, #6
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; CHECK-GI-NEXT: ret
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%tmp = call i4 @llvm.smul.fix.i4(i4 %x, i4 %y, i32 2)
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ret i4 %tmp
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}
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;; These result in regular integer multiplication
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define i32 @func4(i32 %x, i32 %y) nounwind {
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; CHECK-LABEL: func4:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mul w0, w0, w1
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; CHECK-NEXT: ret
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%tmp = call i32 @llvm.smul.fix.i32(i32 %x, i32 %y, i32 0)
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ret i32 %tmp
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}
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define i64 @func5(i64 %x, i64 %y) {
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; CHECK-LABEL: func5:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mul x0, x0, x1
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; CHECK-NEXT: ret
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%tmp = call i64 @llvm.smul.fix.i64(i64 %x, i64 %y, i32 0)
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ret i64 %tmp
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}
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define i4 @func6(i4 %x, i4 %y) nounwind {
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; CHECK-SD-LABEL: func6:
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; CHECK-SD: // %bb.0:
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; CHECK-SD-NEXT: sbfx w8, w1, #0, #4
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; CHECK-SD-NEXT: sbfx w9, w0, #0, #4
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; CHECK-SD-NEXT: mul w0, w9, w8
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: func6:
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; CHECK-GI: // %bb.0:
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; CHECK-GI-NEXT: mul w0, w0, w1
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; CHECK-GI-NEXT: ret
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%tmp = call i4 @llvm.smul.fix.i4(i4 %x, i4 %y, i32 0)
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ret i4 %tmp
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}
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define i64 @func7(i64 %x, i64 %y) nounwind {
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; CHECK-SD-LABEL: func7:
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; CHECK-SD: // %bb.0:
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; CHECK-SD-NEXT: mul x8, x0, x1
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; CHECK-SD-NEXT: smulh x9, x0, x1
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; CHECK-SD-NEXT: extr x0, x9, x8, #32
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: func7:
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; CHECK-GI: // %bb.0:
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; CHECK-GI-NEXT: umulh x8, x0, x1
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; CHECK-GI-NEXT: asr x9, x1, #63
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; CHECK-GI-NEXT: mul x10, x0, x1
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; CHECK-GI-NEXT: madd x8, x0, x9, x8
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; CHECK-GI-NEXT: asr x9, x0, #63
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; CHECK-GI-NEXT: madd x8, x9, x1, x8
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; CHECK-GI-NEXT: extr x0, x8, x10, #32
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; CHECK-GI-NEXT: ret
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%tmp = call i64 @llvm.smul.fix.i64(i64 %x, i64 %y, i32 32)
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ret i64 %tmp
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}
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define i64 @func8(i64 %x, i64 %y) nounwind {
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; CHECK-SD-LABEL: func8:
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; CHECK-SD: // %bb.0:
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; CHECK-SD-NEXT: mul x8, x0, x1
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; CHECK-SD-NEXT: smulh x9, x0, x1
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; CHECK-SD-NEXT: extr x0, x9, x8, #63
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: func8:
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; CHECK-GI: // %bb.0:
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; CHECK-GI-NEXT: umulh x8, x0, x1
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; CHECK-GI-NEXT: asr x9, x1, #63
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; CHECK-GI-NEXT: mul x10, x0, x1
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; CHECK-GI-NEXT: madd x8, x0, x9, x8
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; CHECK-GI-NEXT: asr x9, x0, #63
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; CHECK-GI-NEXT: madd x8, x9, x1, x8
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; CHECK-GI-NEXT: extr x0, x8, x10, #63
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; CHECK-GI-NEXT: ret
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%tmp = call i64 @llvm.smul.fix.i64(i64 %x, i64 %y, i32 63)
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ret i64 %tmp
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}
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define <2 x i32> @smulfix_2xi32_0(<2 x i32> %x, <2 x i32> %y) nounwind {
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; CHECK-LABEL: smulfix_2xi32_0:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mul v0.2s, v0.2s, v1.2s
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; CHECK-NEXT: ret
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%tmp = call <2 x i32> @llvm.smul.fix.v2i32(<2 x i32> %x, <2 x i32> %y, i32 0)
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ret <2 x i32> %tmp
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}
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define <4 x i32> @smulfix_4xi32_0(<4 x i32> %x, <4 x i32> %y) nounwind {
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; CHECK-LABEL: smulfix_4xi32_0:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mul v0.4s, v0.4s, v1.4s
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; CHECK-NEXT: ret
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%tmp = call <4 x i32> @llvm.smul.fix.v4i32(<4 x i32> %x, <4 x i32> %y, i32 0)
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ret <4 x i32> %tmp
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}
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define <4 x i32> @smulfix_4xi32(<4 x i32> %1, <4 x i32> %2) {
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; CHECK-SD-LABEL: smulfix_4xi32:
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; CHECK-SD: // %bb.0:
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; CHECK-SD-NEXT: smull2 v2.2d, v0.4s, v1.4s
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; CHECK-SD-NEXT: smull v3.2d, v0.2s, v1.2s
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; CHECK-SD-NEXT: mul v1.4s, v0.4s, v1.4s
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; CHECK-SD-NEXT: uzp2 v2.4s, v3.4s, v2.4s
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; CHECK-SD-NEXT: shl v0.4s, v2.4s, #17
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; CHECK-SD-NEXT: usra v0.4s, v1.4s, #15
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: smulfix_4xi32:
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; CHECK-GI: // %bb.0:
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; CHECK-GI-NEXT: smull v2.2d, v0.2s, v1.2s
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; CHECK-GI-NEXT: smull2 v1.2d, v0.4s, v1.4s
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; CHECK-GI-NEXT: shrn v0.2s, v2.2d, #15
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; CHECK-GI-NEXT: shrn2 v0.4s, v1.2d, #15
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; CHECK-GI-NEXT: ret
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%m = call <4 x i32> @llvm.smul.fix.v4i32(<4 x i32> %1, <4 x i32> %2, i32 15)
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ret <4 x i32> %m
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}
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define <4 x i64> @smulfix_4xi64(<4 x i64> %x, <4 x i64> %y) nounwind {
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; CHECK-SD-LABEL: smulfix_4xi64:
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; CHECK-SD: // %bb.0:
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; CHECK-SD-NEXT: mov x8, v2.d[1]
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; CHECK-SD-NEXT: mov x9, v0.d[1]
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; CHECK-SD-NEXT: fmov x10, d2
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; CHECK-SD-NEXT: fmov x11, d0
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; CHECK-SD-NEXT: mov x14, v3.d[1]
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; CHECK-SD-NEXT: mov x15, v1.d[1]
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; CHECK-SD-NEXT: mul x12, x11, x10
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; CHECK-SD-NEXT: mul x13, x9, x8
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; CHECK-SD-NEXT: smulh x8, x9, x8
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; CHECK-SD-NEXT: smulh x9, x11, x10
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; CHECK-SD-NEXT: fmov x10, d3
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; CHECK-SD-NEXT: fmov x11, d1
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; CHECK-SD-NEXT: mul x16, x11, x10
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; CHECK-SD-NEXT: extr x8, x8, x13, #32
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; CHECK-SD-NEXT: smulh x10, x11, x10
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; CHECK-SD-NEXT: extr x9, x9, x12, #32
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; CHECK-SD-NEXT: mul x11, x15, x14
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; CHECK-SD-NEXT: fmov d0, x9
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; CHECK-SD-NEXT: smulh x14, x15, x14
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; CHECK-SD-NEXT: extr x10, x10, x16, #32
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; CHECK-SD-NEXT: mov v0.d[1], x8
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; CHECK-SD-NEXT: fmov d1, x10
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; CHECK-SD-NEXT: extr x11, x14, x11, #32
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; CHECK-SD-NEXT: mov v1.d[1], x11
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: smulfix_4xi64:
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; CHECK-GI: // %bb.0:
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; CHECK-GI-NEXT: fmov x8, d0
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; CHECK-GI-NEXT: fmov x9, d2
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; CHECK-GI-NEXT: mov d0, v0.d[1]
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; CHECK-GI-NEXT: mov d2, v2.d[1]
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; CHECK-GI-NEXT: umulh x10, x8, x9
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; CHECK-GI-NEXT: asr x11, x9, #63
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; CHECK-GI-NEXT: fmov x13, d2
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; CHECK-GI-NEXT: mul x12, x8, x9
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; CHECK-GI-NEXT: madd x10, x8, x11, x10
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; CHECK-GI-NEXT: fmov x11, d0
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; CHECK-GI-NEXT: asr x8, x8, #63
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; CHECK-GI-NEXT: asr x15, x13, #63
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; CHECK-GI-NEXT: mov d0, v1.d[1]
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; CHECK-GI-NEXT: umulh x14, x11, x13
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; CHECK-GI-NEXT: madd x8, x8, x9, x10
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; CHECK-GI-NEXT: asr x10, x11, #63
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; CHECK-GI-NEXT: madd x9, x11, x15, x14
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; CHECK-GI-NEXT: mul x11, x11, x13
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; CHECK-GI-NEXT: extr x8, x8, x12, #32
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; CHECK-GI-NEXT: madd x9, x10, x13, x9
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; CHECK-GI-NEXT: fmov x10, d1
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; CHECK-GI-NEXT: fmov x13, d3
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; CHECK-GI-NEXT: mov d1, v3.d[1]
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; CHECK-GI-NEXT: umulh x14, x10, x13
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; CHECK-GI-NEXT: asr x15, x13, #63
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; CHECK-GI-NEXT: fmov x17, d1
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; CHECK-GI-NEXT: mul x16, x10, x13
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; CHECK-GI-NEXT: extr x9, x9, x11, #32
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; CHECK-GI-NEXT: madd x14, x10, x15, x14
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; CHECK-GI-NEXT: fmov x15, d0
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; CHECK-GI-NEXT: asr x10, x10, #63
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; CHECK-GI-NEXT: asr x0, x17, #63
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; CHECK-GI-NEXT: fmov d0, x8
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; CHECK-GI-NEXT: umulh x18, x15, x17
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; CHECK-GI-NEXT: mov v0.d[1], x9
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; CHECK-GI-NEXT: madd x10, x10, x13, x14
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; CHECK-GI-NEXT: asr x14, x15, #63
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; CHECK-GI-NEXT: madd x13, x15, x0, x18
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; CHECK-GI-NEXT: mul x15, x15, x17
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; CHECK-GI-NEXT: extr x10, x10, x16, #32
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; CHECK-GI-NEXT: madd x13, x14, x17, x13
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; CHECK-GI-NEXT: fmov d1, x10
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; CHECK-GI-NEXT: extr x11, x13, x15, #32
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; CHECK-GI-NEXT: mov v1.d[1], x11
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; CHECK-GI-NEXT: ret
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%tmp = call <4 x i64> @llvm.smul.fix.v4i64(<4 x i64> %x, <4 x i64> %y, i32 32)
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ret <4 x i64> %tmp
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}
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define <4 x i16> @widemul(<4 x i16> %x, <4 x i16> %y) nounwind {
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; CHECK-SD-LABEL: widemul:
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; CHECK-SD: // %bb.0:
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; CHECK-SD-NEXT: smull v0.4s, v0.4h, v1.4h
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; CHECK-SD-NEXT: shrn v1.4h, v0.4s, #16
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; CHECK-SD-NEXT: xtn v2.4h, v0.4s
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; CHECK-SD-NEXT: shl v0.4h, v1.4h, #14
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; CHECK-SD-NEXT: usra v0.4h, v2.4h, #2
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: widemul:
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; CHECK-GI: // %bb.0:
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; CHECK-GI-NEXT: smull v0.4s, v0.4h, v1.4h
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; CHECK-GI-NEXT: shrn v0.4h, v0.4s, #2
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; CHECK-GI-NEXT: ret
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%tmp = call <4 x i16> @llvm.smul.fix.v4i16(<4 x i16> %x, <4 x i16> %y, i32 2)
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ret <4 x i16> %tmp
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}
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