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108 lines
3.8 KiB
YAML
108 lines
3.8 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
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# RUN: llc -mtriple=aarch64 -run-pass=aarch64-srlt-define-superregs -enable-subreg-liveness -o - %s | FileCheck %s
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--- |
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target triple = "aarch64"
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define void @test_implicit_def_w1_to_x1() { entry: unreachable }
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define void @test_implicit_def_dead_w1_to_dead_x1() { entry: unreachable }
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define void @test_implicit_def_d0_to_q0_and_d1_to_q1() { entry: unreachable }
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define void @test_implicit_def_d0_d1_d2_to_q0_q1_q2() { entry: unreachable }
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define void @test_implicit_def_d0_d1_d2_to_z0_z1_z2_with_sve() "target-features"="+sve" { entry: unreachable }
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---
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name: test_implicit_def_w1_to_x1
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isSSA: false
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $x1
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; CHECK-LABEL: name: test_implicit_def_w1_to_x1
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; CHECK: liveins: $x1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: renamable $x0 = COPY $x1
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; CHECK-NEXT: renamable $w1 = ORRWrr $wzr, renamable $w0, implicit-def renamable $x1
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; CHECK-NEXT: RET_ReallyLR implicit $x1, implicit $x0
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renamable $x0 = COPY $x1
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renamable $w1 = ORRWrr $wzr, renamable $w0
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RET_ReallyLR implicit $x1, implicit $x0
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...
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---
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name: test_implicit_def_dead_w1_to_dead_x1
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isSSA: false
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $x1
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; CHECK-LABEL: name: test_implicit_def_dead_w1_to_dead_x1
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; CHECK: liveins: $x1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: renamable $x0 = COPY $x1
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; CHECK-NEXT: dead renamable $w1 = ORRWrr $wzr, renamable $w0, implicit-def dead renamable $x1
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; CHECK-NEXT: RET_ReallyLR implicit $x0
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renamable $x0 = COPY $x1
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dead renamable $w1 = ORRWrr $wzr, renamable $w0
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RET_ReallyLR implicit $x0
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...
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---
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name: test_implicit_def_d0_to_q0_and_d1_to_q1
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isSSA: false
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $d0, $d1, $x1
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; CHECK-LABEL: name: test_implicit_def_d0_to_q0_and_d1_to_q1
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; CHECK: liveins: $d0, $d1, $x1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: early-clobber $x1, renamable $d0, renamable $d1 = LDPDpre renamable $x1, 16, implicit-def renamable $q0, implicit-def renamable $q1 :: (load (s64))
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; CHECK-NEXT: STPDi renamable $d0, renamable $d1, renamable $x1, 0 :: (store (s64))
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; CHECK-NEXT: RET undef $lr
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early-clobber $x1, renamable $d0, renamable $d1 = LDPDpre renamable $x1, 16 :: (load (s64))
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STPDi renamable $d0, renamable $d1, renamable $x1, 0 :: (store (s64))
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RET undef $lr
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...
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---
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name: test_implicit_def_d0_d1_d2_to_q0_q1_q2
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isSSA: false
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tracksRegLiveness: true
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machineFunctionInfo: {}
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body: |
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bb.0.entry:
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liveins: $x0, $x1, $lr, $fp
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; CHECK-LABEL: name: test_implicit_def_d0_d1_d2_to_q0_q1_q2
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; CHECK: liveins: $x0, $x1, $lr, $fp
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: renamable $x0, renamable $d0_d1_d2 = LD3Threev8b_POST killed renamable $x0, $xzr, implicit-def renamable $q0_q1_q2
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; CHECK-NEXT: FAKE_USE $x0
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; CHECK-NEXT: FAKE_USE $d0_d1_d2
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; CHECK-NEXT: RET undef $lr
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renamable $x0, renamable $d0_d1_d2 = LD3Threev8b_POST killed renamable $x0, $xzr
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FAKE_USE $x0
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FAKE_USE $d0_d1_d2
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RET undef $lr
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...
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---
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name: test_implicit_def_d0_d1_d2_to_z0_z1_z2_with_sve
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isSSA: false
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tracksRegLiveness: true
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machineFunctionInfo: {}
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body: |
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bb.0.entry:
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liveins: $x0, $x1, $lr, $fp
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; CHECK-LABEL: name: test_implicit_def_d0_d1_d2_to_z0_z1_z2_with_sve
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; CHECK: liveins: $x0, $x1, $lr, $fp
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: renamable $x0, renamable $d0_d1_d2 = LD3Threev8b_POST killed renamable $x0, $xzr, implicit-def renamable $z0_z1_z2
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; CHECK-NEXT: FAKE_USE $x0
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; CHECK-NEXT: FAKE_USE $d0_d1_d2
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; CHECK-NEXT: RET undef $lr
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renamable $x0, renamable $d0_d1_d2 = LD3Threev8b_POST killed renamable $x0, $xzr
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FAKE_USE $x0
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FAKE_USE $d0_d1_d2
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RET undef $lr
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...
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