derek.holloway
7502bf64a4
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43 lines
1.4 KiB
LLVM
43 lines
1.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s | FileCheck %s
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target triple = "aarch64-unknown-linux-gnu"
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;
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; ADR
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; Tests adr z0.s, [z0.s, z0.s, lsl #<1,2,3>]
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; Other formats are tested in llvm/test/CodeGen/AArch64/sve-gep.ll
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;
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define <vscale x 4 x i32> @adr_32bit_lsl1(<vscale x 4 x i32> %base, <vscale x 4 x i32> %idx) #0 {
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; CHECK-LABEL: adr_32bit_lsl1:
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; CHECK: // %bb.0:
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; CHECK-NEXT: adr z0.s, [z0.s, z1.s, lsl #1]
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; CHECK-NEXT: ret
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%offset = shl <vscale x 4 x i32> %idx, splat (i32 1)
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%address = add <vscale x 4 x i32> %base, %offset
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ret <vscale x 4 x i32> %address
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}
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define <vscale x 4 x i32> @adr_32bit_lsl2(<vscale x 4 x i32> %base, <vscale x 4 x i32> %idx) #0 {
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; CHECK-LABEL: adr_32bit_lsl2:
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; CHECK: // %bb.0:
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; CHECK-NEXT: adr z0.s, [z0.s, z1.s, lsl #2]
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; CHECK-NEXT: ret
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%offset = shl <vscale x 4 x i32> %idx, splat (i32 2)
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%address = add <vscale x 4 x i32> %base, %offset
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ret <vscale x 4 x i32> %address
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}
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define <vscale x 4 x i32> @adr_32bit_lsl3(<vscale x 4 x i32> %base, <vscale x 4 x i32> %idx) #0 {
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; CHECK-LABEL: adr_32bit_lsl3:
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; CHECK: // %bb.0:
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; CHECK-NEXT: adr z0.s, [z0.s, z1.s, lsl #3]
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; CHECK-NEXT: ret
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%offset = shl <vscale x 4 x i32> %idx, splat (i32 3)
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%address = add <vscale x 4 x i32> %base, %offset
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ret <vscale x 4 x i32> %address
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}
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attributes #0 = { "target-features"="+sve" }
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