derek.holloway
7502bf64a4
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246 lines
8.7 KiB
LLVM
246 lines
8.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc -mattr=+sve < %s | FileCheck %s --check-prefixes=CHECK,NOBF16
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; RUN: llc -mattr=+sve,+bf16 < %s | FileCheck %s --check-prefixes=CHECK,BF16
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; RUN: llc -mattr=+sme -force-streaming < %s | FileCheck %s --check-prefixes=CHECK,BF16
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target triple = "aarch64-unknown-linux-gnu"
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; NOTE: "fptrunc <# x double> to <# x bfloat>" is not supported because SVE
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; lacks a down convert that rounds to odd. Such IR will trigger the usual
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; failure (crash) when attempting to unroll a scalable vector.
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define <vscale x 2 x float> @fpext_nxv2bf16_to_nxv2f32(<vscale x 2 x bfloat> %a) {
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; CHECK-LABEL: fpext_nxv2bf16_to_nxv2f32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: lsl z0.s, z0.s, #16
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; CHECK-NEXT: ret
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%res = fpext <vscale x 2 x bfloat> %a to <vscale x 2 x float>
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ret <vscale x 2 x float> %res
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}
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define <vscale x 4 x float> @fpext_nxv4bf16_to_nxv4f32(<vscale x 4 x bfloat> %a) {
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; CHECK-LABEL: fpext_nxv4bf16_to_nxv4f32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: lsl z0.s, z0.s, #16
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; CHECK-NEXT: ret
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%res = fpext <vscale x 4 x bfloat> %a to <vscale x 4 x float>
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ret <vscale x 4 x float> %res
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}
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define <vscale x 8 x float> @fpext_nxv8bf16_to_nxv8f32(<vscale x 8 x bfloat> %a) {
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; CHECK-LABEL: fpext_nxv8bf16_to_nxv8f32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: movi v1.2d, #0000000000000000
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; CHECK-NEXT: zip1 z2.h, z1.h, z0.h
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; CHECK-NEXT: zip2 z1.h, z1.h, z0.h
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; CHECK-NEXT: mov z0.d, z2.d
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; CHECK-NEXT: ret
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%res = fpext <vscale x 8 x bfloat> %a to <vscale x 8 x float>
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ret <vscale x 8 x float> %res
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}
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define <vscale x 2 x double> @fpext_nxv2bf16_to_nxv2f64(<vscale x 2 x bfloat> %a) {
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; CHECK-LABEL: fpext_nxv2bf16_to_nxv2f64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: lsl z0.s, z0.s, #16
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; CHECK-NEXT: ptrue p0.d
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; CHECK-NEXT: fcvt z0.d, p0/m, z0.s
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; CHECK-NEXT: ret
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%res = fpext <vscale x 2 x bfloat> %a to <vscale x 2 x double>
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ret <vscale x 2 x double> %res
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}
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define <vscale x 4 x double> @fpext_nxv4bf16_to_nxv4f64(<vscale x 4 x bfloat> %a) {
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; CHECK-LABEL: fpext_nxv4bf16_to_nxv4f64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: uunpklo z1.d, z0.s
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; CHECK-NEXT: uunpkhi z0.d, z0.s
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; CHECK-NEXT: ptrue p0.d
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; CHECK-NEXT: lsl z1.s, z1.s, #16
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; CHECK-NEXT: lsl z2.s, z0.s, #16
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; CHECK-NEXT: movprfx z0, z1
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; CHECK-NEXT: fcvt z0.d, p0/m, z1.s
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; CHECK-NEXT: movprfx z1, z2
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; CHECK-NEXT: fcvt z1.d, p0/m, z2.s
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; CHECK-NEXT: ret
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%res = fpext <vscale x 4 x bfloat> %a to <vscale x 4 x double>
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ret <vscale x 4 x double> %res
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}
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define <vscale x 8 x double> @fpext_nxv8bf16_to_nxv8f64(<vscale x 8 x bfloat> %a) {
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; CHECK-LABEL: fpext_nxv8bf16_to_nxv8f64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: uunpklo z1.s, z0.h
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; CHECK-NEXT: uunpkhi z0.s, z0.h
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; CHECK-NEXT: ptrue p0.d
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; CHECK-NEXT: uunpklo z2.d, z1.s
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; CHECK-NEXT: uunpkhi z1.d, z1.s
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; CHECK-NEXT: uunpklo z3.d, z0.s
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; CHECK-NEXT: uunpkhi z0.d, z0.s
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; CHECK-NEXT: lsl z1.s, z1.s, #16
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; CHECK-NEXT: lsl z2.s, z2.s, #16
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; CHECK-NEXT: lsl z3.s, z3.s, #16
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; CHECK-NEXT: lsl z4.s, z0.s, #16
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; CHECK-NEXT: fcvt z1.d, p0/m, z1.s
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; CHECK-NEXT: movprfx z0, z2
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; CHECK-NEXT: fcvt z0.d, p0/m, z2.s
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; CHECK-NEXT: movprfx z2, z3
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; CHECK-NEXT: fcvt z2.d, p0/m, z3.s
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; CHECK-NEXT: movprfx z3, z4
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; CHECK-NEXT: fcvt z3.d, p0/m, z4.s
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; CHECK-NEXT: ret
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%res = fpext <vscale x 8 x bfloat> %a to <vscale x 8 x double>
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ret <vscale x 8 x double> %res
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}
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define <vscale x 2 x bfloat> @fptrunc_nxv2f32_to_nxv2bf16(<vscale x 2 x float> %a) {
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; NOBF16-LABEL: fptrunc_nxv2f32_to_nxv2bf16:
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; NOBF16: // %bb.0:
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; NOBF16-NEXT: mov z1.s, #32767 // =0x7fff
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; NOBF16-NEXT: lsr z2.s, z0.s, #16
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; NOBF16-NEXT: ptrue p0.d
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; NOBF16-NEXT: fcmuo p0.s, p0/z, z0.s, z0.s
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; NOBF16-NEXT: and z2.s, z2.s, #0x1
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; NOBF16-NEXT: add z1.s, z0.s, z1.s
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; NOBF16-NEXT: orr z0.s, z0.s, #0x400000
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; NOBF16-NEXT: add z1.s, z2.s, z1.s
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; NOBF16-NEXT: sel z0.s, p0, z0.s, z1.s
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; NOBF16-NEXT: lsr z0.s, z0.s, #16
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; NOBF16-NEXT: ret
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;
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; BF16-LABEL: fptrunc_nxv2f32_to_nxv2bf16:
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; BF16: // %bb.0:
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; BF16-NEXT: ptrue p0.d
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; BF16-NEXT: bfcvt z0.h, p0/m, z0.s
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; BF16-NEXT: ret
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%res = fptrunc <vscale x 2 x float> %a to <vscale x 2 x bfloat>
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ret <vscale x 2 x bfloat> %res
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}
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define <vscale x 2 x bfloat> @fptrunc_nxv2f32_to_nxv2bf16_nnan(<vscale x 2 x float> %a) {
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; NOBF16-LABEL: fptrunc_nxv2f32_to_nxv2bf16_nnan:
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; NOBF16: // %bb.0:
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; NOBF16-NEXT: mov z1.s, #32767 // =0x7fff
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; NOBF16-NEXT: lsr z2.s, z0.s, #16
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; NOBF16-NEXT: and z2.s, z2.s, #0x1
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; NOBF16-NEXT: add z0.s, z0.s, z1.s
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; NOBF16-NEXT: add z0.s, z2.s, z0.s
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; NOBF16-NEXT: lsr z0.s, z0.s, #16
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; NOBF16-NEXT: ret
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;
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; BF16-LABEL: fptrunc_nxv2f32_to_nxv2bf16_nnan:
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; BF16: // %bb.0:
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; BF16-NEXT: ptrue p0.d
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; BF16-NEXT: bfcvt z0.h, p0/m, z0.s
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; BF16-NEXT: ret
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%res = fptrunc nnan <vscale x 2 x float> %a to <vscale x 2 x bfloat>
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ret <vscale x 2 x bfloat> %res
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}
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define <vscale x 4 x bfloat> @fptrunc_nxv4f32_to_nxv4bf16(<vscale x 4 x float> %a) {
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; NOBF16-LABEL: fptrunc_nxv4f32_to_nxv4bf16:
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; NOBF16: // %bb.0:
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; NOBF16-NEXT: mov z1.s, #32767 // =0x7fff
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; NOBF16-NEXT: lsr z2.s, z0.s, #16
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; NOBF16-NEXT: ptrue p0.s
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; NOBF16-NEXT: fcmuo p0.s, p0/z, z0.s, z0.s
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; NOBF16-NEXT: and z2.s, z2.s, #0x1
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; NOBF16-NEXT: add z1.s, z0.s, z1.s
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; NOBF16-NEXT: orr z0.s, z0.s, #0x400000
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; NOBF16-NEXT: add z1.s, z2.s, z1.s
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; NOBF16-NEXT: sel z0.s, p0, z0.s, z1.s
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; NOBF16-NEXT: lsr z0.s, z0.s, #16
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; NOBF16-NEXT: ret
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;
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; BF16-LABEL: fptrunc_nxv4f32_to_nxv4bf16:
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; BF16: // %bb.0:
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; BF16-NEXT: ptrue p0.s
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; BF16-NEXT: bfcvt z0.h, p0/m, z0.s
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; BF16-NEXT: ret
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%res = fptrunc <vscale x 4 x float> %a to <vscale x 4 x bfloat>
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ret <vscale x 4 x bfloat> %res
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}
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define <vscale x 4 x bfloat> @fptrunc_nxv4f32_to_nxv4bf16_nnan(<vscale x 4 x float> %a) {
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; NOBF16-LABEL: fptrunc_nxv4f32_to_nxv4bf16_nnan:
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; NOBF16: // %bb.0:
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; NOBF16-NEXT: mov z1.s, #32767 // =0x7fff
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; NOBF16-NEXT: lsr z2.s, z0.s, #16
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; NOBF16-NEXT: and z2.s, z2.s, #0x1
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; NOBF16-NEXT: add z0.s, z0.s, z1.s
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; NOBF16-NEXT: add z0.s, z2.s, z0.s
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; NOBF16-NEXT: lsr z0.s, z0.s, #16
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; NOBF16-NEXT: ret
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;
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; BF16-LABEL: fptrunc_nxv4f32_to_nxv4bf16_nnan:
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; BF16: // %bb.0:
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; BF16-NEXT: ptrue p0.s
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; BF16-NEXT: bfcvt z0.h, p0/m, z0.s
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; BF16-NEXT: ret
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%res = fptrunc nnan <vscale x 4 x float> %a to <vscale x 4 x bfloat>
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ret <vscale x 4 x bfloat> %res
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}
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define <vscale x 8 x bfloat> @fptrunc_nxv8f32_to_nxv8bf16(<vscale x 8 x float> %a) {
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; NOBF16-LABEL: fptrunc_nxv8f32_to_nxv8bf16:
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; NOBF16: // %bb.0:
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; NOBF16-NEXT: mov z2.s, #32767 // =0x7fff
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; NOBF16-NEXT: lsr z3.s, z1.s, #16
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; NOBF16-NEXT: lsr z4.s, z0.s, #16
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; NOBF16-NEXT: ptrue p0.s
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; NOBF16-NEXT: and z3.s, z3.s, #0x1
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; NOBF16-NEXT: and z4.s, z4.s, #0x1
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; NOBF16-NEXT: add z5.s, z1.s, z2.s
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; NOBF16-NEXT: add z2.s, z0.s, z2.s
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; NOBF16-NEXT: fcmuo p1.s, p0/z, z1.s, z1.s
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; NOBF16-NEXT: orr z1.s, z1.s, #0x400000
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; NOBF16-NEXT: fcmuo p0.s, p0/z, z0.s, z0.s
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; NOBF16-NEXT: orr z0.s, z0.s, #0x400000
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; NOBF16-NEXT: add z3.s, z3.s, z5.s
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; NOBF16-NEXT: add z2.s, z4.s, z2.s
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; NOBF16-NEXT: sel z1.s, p1, z1.s, z3.s
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; NOBF16-NEXT: sel z0.s, p0, z0.s, z2.s
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; NOBF16-NEXT: lsr z1.s, z1.s, #16
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; NOBF16-NEXT: lsr z0.s, z0.s, #16
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; NOBF16-NEXT: uzp1 z0.h, z0.h, z1.h
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; NOBF16-NEXT: ret
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;
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; BF16-LABEL: fptrunc_nxv8f32_to_nxv8bf16:
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; BF16: // %bb.0:
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; BF16-NEXT: ptrue p0.s
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; BF16-NEXT: bfcvt z1.h, p0/m, z1.s
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; BF16-NEXT: bfcvt z0.h, p0/m, z0.s
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; BF16-NEXT: uzp1 z0.h, z0.h, z1.h
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; BF16-NEXT: ret
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%res = fptrunc <vscale x 8 x float> %a to <vscale x 8 x bfloat>
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ret <vscale x 8 x bfloat> %res
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}
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define <vscale x 8 x bfloat> @fptrunc_nxv8f32_to_nxv8bf16_nnan(<vscale x 8 x float> %a) {
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; NOBF16-LABEL: fptrunc_nxv8f32_to_nxv8bf16_nnan:
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; NOBF16: // %bb.0:
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; NOBF16-NEXT: mov z2.s, #32767 // =0x7fff
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; NOBF16-NEXT: lsr z3.s, z1.s, #16
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; NOBF16-NEXT: lsr z4.s, z0.s, #16
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; NOBF16-NEXT: and z3.s, z3.s, #0x1
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; NOBF16-NEXT: and z4.s, z4.s, #0x1
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; NOBF16-NEXT: add z1.s, z1.s, z2.s
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; NOBF16-NEXT: add z0.s, z0.s, z2.s
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; NOBF16-NEXT: add z1.s, z3.s, z1.s
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; NOBF16-NEXT: add z0.s, z4.s, z0.s
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; NOBF16-NEXT: lsr z1.s, z1.s, #16
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; NOBF16-NEXT: lsr z0.s, z0.s, #16
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; NOBF16-NEXT: uzp1 z0.h, z0.h, z1.h
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; NOBF16-NEXT: ret
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;
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; BF16-LABEL: fptrunc_nxv8f32_to_nxv8bf16_nnan:
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; BF16: // %bb.0:
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; BF16-NEXT: ptrue p0.s
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; BF16-NEXT: bfcvt z1.h, p0/m, z1.s
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; BF16-NEXT: bfcvt z0.h, p0/m, z0.s
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; BF16-NEXT: uzp1 z0.h, z0.h, z1.h
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; BF16-NEXT: ret
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%res = fptrunc nnan <vscale x 8 x float> %a to <vscale x 8 x bfloat>
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ret <vscale x 8 x bfloat> %res
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}
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