derek.holloway
7502bf64a4
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206 lines
8.0 KiB
LLVM
206 lines
8.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
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; RUN: llc < %s | FileCheck %s
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; RUN: llc -mattr=+disable-distinct-predicate-dst-reg < %s | FileCheck %s --check-prefix=DISABLE-HINT
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target triple = "aarch64"
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;
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; Test that the destination register of the match/cmp instruction is different
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; from the governing predicate register.
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;
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define void @match_hint_distinct_pg_b(ptr %ptr, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) #0 {
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; CHECK-LABEL: match_hint_distinct_pg_b:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.b
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; CHECK-NEXT: match p1.b, p0/z, z0.b, z1.b
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; CHECK-NEXT: st1b { z0.b }, p1, [x0]
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; CHECK-NEXT: ret
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;
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; DISABLE-HINT-LABEL: match_hint_distinct_pg_b:
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; DISABLE-HINT: // %bb.0:
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; DISABLE-HINT-NEXT: ptrue p0.b
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; DISABLE-HINT-NEXT: match p0.b, p0/z, z0.b, z1.b
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; DISABLE-HINT-NEXT: st1b { z0.b }, p0, [x0]
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; DISABLE-HINT-NEXT: ret
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%match = tail call <vscale x 16 x i1> @llvm.aarch64.sve.match.nxv16i8(<vscale x 16 x i1> splat (i1 true), <vscale x 16 x i8> %a, <vscale x 16 x i8> %b)
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call void @llvm.masked.store(<vscale x 16 x i8> %a, ptr %ptr, <vscale x 16 x i1> %match)
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ret void
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}
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define void @match_hint_distinct_pg_h(ptr %ptr, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b) #0 {
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; CHECK-LABEL: match_hint_distinct_pg_h:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.h
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; CHECK-NEXT: match p1.h, p0/z, z0.h, z1.h
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; CHECK-NEXT: st1h { z0.h }, p1, [x0]
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; CHECK-NEXT: ret
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;
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; DISABLE-HINT-LABEL: match_hint_distinct_pg_h:
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; DISABLE-HINT: // %bb.0:
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; DISABLE-HINT-NEXT: ptrue p0.h
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; DISABLE-HINT-NEXT: match p0.h, p0/z, z0.h, z1.h
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; DISABLE-HINT-NEXT: st1h { z0.h }, p0, [x0]
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; DISABLE-HINT-NEXT: ret
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%match = tail call <vscale x 8 x i1> @llvm.aarch64.sve.match.nxv16i8(<vscale x 8 x i1> splat (i1 true), <vscale x 8 x i16> %a, <vscale x 8 x i16> %b)
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call void @llvm.masked.store(<vscale x 8 x i16> %a, ptr %ptr, <vscale x 8 x i1> %match)
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ret void
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}
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define void @cmp_hint_distinct_pg_b(ptr %ptr, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) #0 {
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; CHECK-LABEL: cmp_hint_distinct_pg_b:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.b
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; CHECK-NEXT: cmpeq p1.b, p0/z, z0.b, z1.b
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; CHECK-NEXT: st1b { z0.b }, p1, [x0]
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; CHECK-NEXT: ret
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;
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; DISABLE-HINT-LABEL: cmp_hint_distinct_pg_b:
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; DISABLE-HINT: // %bb.0:
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; DISABLE-HINT-NEXT: ptrue p0.b
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; DISABLE-HINT-NEXT: cmpeq p0.b, p0/z, z0.b, z1.b
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; DISABLE-HINT-NEXT: st1b { z0.b }, p0, [x0]
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; DISABLE-HINT-NEXT: ret
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%cmp = icmp eq <vscale x 16 x i8> %a, %b
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call void @llvm.masked.store(<vscale x 16 x i8> %a, ptr %ptr, <vscale x 16 x i1> %cmp)
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ret void
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}
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define void @cmp_hint_distinct_pg_h(ptr %ptr, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b) #0 {
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; CHECK-LABEL: cmp_hint_distinct_pg_h:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.h
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; CHECK-NEXT: cmpeq p1.h, p0/z, z0.h, z1.h
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; CHECK-NEXT: st1h { z0.h }, p1, [x0]
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; CHECK-NEXT: ret
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;
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; DISABLE-HINT-LABEL: cmp_hint_distinct_pg_h:
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; DISABLE-HINT: // %bb.0:
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; DISABLE-HINT-NEXT: ptrue p0.h
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; DISABLE-HINT-NEXT: cmpeq p0.h, p0/z, z0.h, z1.h
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; DISABLE-HINT-NEXT: st1h { z0.h }, p0, [x0]
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; DISABLE-HINT-NEXT: ret
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%cmp = icmp eq <vscale x 8 x i16> %a, %b
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call void @llvm.masked.store(<vscale x 8 x i16> %a, ptr %ptr, <vscale x 8 x i1> %cmp)
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ret void
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}
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define void @cmp_hint_distinct_pg_s(ptr %ptr, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b) #0 {
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; CHECK-LABEL: cmp_hint_distinct_pg_s:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.s
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; CHECK-NEXT: cmpeq p1.s, p0/z, z0.s, z1.s
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; CHECK-NEXT: st1w { z0.s }, p1, [x0]
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; CHECK-NEXT: ret
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;
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; DISABLE-HINT-LABEL: cmp_hint_distinct_pg_s:
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; DISABLE-HINT: // %bb.0:
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; DISABLE-HINT-NEXT: ptrue p0.s
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; DISABLE-HINT-NEXT: cmpeq p0.s, p0/z, z0.s, z1.s
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; DISABLE-HINT-NEXT: st1w { z0.s }, p0, [x0]
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; DISABLE-HINT-NEXT: ret
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%cmp = icmp eq <vscale x 4 x i32> %a, %b
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call void @llvm.masked.store(<vscale x 4 x i32> %a, ptr %ptr, <vscale x 4 x i1> %cmp)
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ret void
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}
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define void @cmp_hint_distinct_pg_d(ptr %ptr, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) #0 {
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; CHECK-LABEL: cmp_hint_distinct_pg_d:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.d
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; CHECK-NEXT: cmpeq p1.d, p0/z, z0.d, z1.d
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; CHECK-NEXT: st1d { z0.d }, p1, [x0]
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; CHECK-NEXT: ret
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;
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; DISABLE-HINT-LABEL: cmp_hint_distinct_pg_d:
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; DISABLE-HINT: // %bb.0:
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; DISABLE-HINT-NEXT: ptrue p0.d
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; DISABLE-HINT-NEXT: cmpeq p0.d, p0/z, z0.d, z1.d
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; DISABLE-HINT-NEXT: st1d { z0.d }, p0, [x0]
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; DISABLE-HINT-NEXT: ret
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%cmp = icmp eq <vscale x 2 x i64> %a, %b
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call void @llvm.masked.store(<vscale x 2 x i64> %a, ptr %ptr, <vscale x 2 x i1> %cmp)
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ret void
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}
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;
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; Also test a case for the wide-element and immediate variants of CMP<>
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;
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define void @wide_cmp_hint_distinct_pg_b(ptr %ptr, <vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 2 x i64> %b) #0 {
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; CHECK-LABEL: wide_cmp_hint_distinct_pg_b:
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; CHECK: // %bb.0:
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; CHECK-NEXT: cmpeq p1.b, p0/z, z0.b, z1.d
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; CHECK-NEXT: st1b { z0.b }, p1, [x0]
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; CHECK-NEXT: ret
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;
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; DISABLE-HINT-LABEL: wide_cmp_hint_distinct_pg_b:
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; DISABLE-HINT: // %bb.0:
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; DISABLE-HINT-NEXT: cmpeq p0.b, p0/z, z0.b, z1.d
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; DISABLE-HINT-NEXT: st1b { z0.b }, p0, [x0]
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; DISABLE-HINT-NEXT: ret
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%cmp = call <vscale x 16 x i1> @llvm.aarch64.sve.cmpeq.wide.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 2 x i64> %b)
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call void @llvm.masked.store(<vscale x 16 x i8> %a, ptr %ptr, <vscale x 16 x i1> %cmp)
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ret void
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}
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define void @imm_cmp_hint_distinct_pg_b(ptr %ptr, <vscale x 16 x i1> %pg, <vscale x 16 x i8> %a) #0 {
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; CHECK-LABEL: imm_cmp_hint_distinct_pg_b:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.b
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; CHECK-NEXT: cmpeq p1.b, p0/z, z0.b, #12
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; CHECK-NEXT: st1b { z0.b }, p1, [x0]
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; CHECK-NEXT: ret
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;
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; DISABLE-HINT-LABEL: imm_cmp_hint_distinct_pg_b:
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; DISABLE-HINT: // %bb.0:
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; DISABLE-HINT-NEXT: ptrue p0.b
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; DISABLE-HINT-NEXT: cmpeq p0.b, p0/z, z0.b, #12
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; DISABLE-HINT-NEXT: st1b { z0.b }, p0, [x0]
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; DISABLE-HINT-NEXT: ret
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%cmp = icmp eq <vscale x 16 x i8> %a, splat(i8 12)
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call void @llvm.masked.store(<vscale x 16 x i8> %a, ptr %ptr, <vscale x 16 x i1> %cmp)
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ret void
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}
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;
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; Some negative tests.
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;
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; Test that no different register is selected if that would introduce a mov.
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define <vscale x 16 x i1> @match_hint_dont_cause_extra_mov(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) #0 {
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; CHECK-LABEL: match_hint_dont_cause_extra_mov:
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; CHECK: // %bb.0:
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; CHECK-NEXT: match p0.b, p0/z, z0.b, z1.b
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; CHECK-NEXT: ret
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;
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; DISABLE-HINT-LABEL: match_hint_dont_cause_extra_mov:
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; DISABLE-HINT: // %bb.0:
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; DISABLE-HINT-NEXT: match p0.b, p0/z, z0.b, z1.b
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; DISABLE-HINT-NEXT: ret
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%match = tail call <vscale x 16 x i1> @llvm.aarch64.sve.match.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b)
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ret <vscale x 16 x i1> %match
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}
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; This is a case that is not yet supported, because at the point of constructing
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; the hint for 'match' the all-true predicate is not yet allocated, so it can't
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; choose a distinct register yet. This case could be support by looking through
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; uses of the ptrue, but that may not be worth it because the ptrue is likely to
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; have more than one use and this seems like an artificial case.
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define <vscale x 16 x i1> @unsupported_because_ptrue_not_yet_allocated(ptr %ptr, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) #0 {
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; CHECK-LABEL: unsupported_because_ptrue_not_yet_allocated:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.b
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; CHECK-NEXT: match p0.b, p0/z, z0.b, z1.b
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; CHECK-NEXT: ret
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;
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; DISABLE-HINT-LABEL: unsupported_because_ptrue_not_yet_allocated:
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; DISABLE-HINT: // %bb.0:
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; DISABLE-HINT-NEXT: ptrue p0.b
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; DISABLE-HINT-NEXT: match p0.b, p0/z, z0.b, z1.b
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; DISABLE-HINT-NEXT: ret
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%match = tail call <vscale x 16 x i1> @llvm.aarch64.sve.match.nxv16i8(<vscale x 16 x i1> splat (i1 true), <vscale x 16 x i8> %a, <vscale x 16 x i8> %b)
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ret <vscale x 16 x i1> %match
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}
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attributes #0 = { "target-features"="+sve2" }
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