derek.holloway
7502bf64a4
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1021 lines
34 KiB
LLVM
1021 lines
34 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -aarch64-sve-vector-bits-min=256 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_256
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; RUN: llc -aarch64-sve-vector-bits-min=512 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_512
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; RUN: llc -aarch64-sve-vector-bits-min=2048 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_512
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target triple = "aarch64-unknown-linux-gnu"
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;
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; FCMP OEQ
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;
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; Don't use SVE for 64-bit vectors.
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define <4 x i16> @fcmp_oeq_v4f16(<4 x half> %op1, <4 x half> %op2) vscale_range(2,0) #0 {
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; CHECK-LABEL: fcmp_oeq_v4f16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: fcmeq v0.4h, v0.4h, v1.4h
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; CHECK-NEXT: ret
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%cmp = fcmp oeq <4 x half> %op1, %op2
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%sext = sext <4 x i1> %cmp to <4 x i16>
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ret <4 x i16> %sext
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}
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; Don't use SVE for 128-bit vectors.
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define <8 x i16> @fcmp_oeq_v8f16(<8 x half> %op1, <8 x half> %op2) vscale_range(2,0) #0 {
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; CHECK-LABEL: fcmp_oeq_v8f16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: fcmeq v0.8h, v0.8h, v1.8h
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; CHECK-NEXT: ret
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%cmp = fcmp oeq <8 x half> %op1, %op2
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%sext = sext <8 x i1> %cmp to <8 x i16>
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ret <8 x i16> %sext
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}
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define void @fcmp_oeq_v16f16(ptr %a, ptr %b, ptr %c) vscale_range(2,0) #0 {
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; CHECK-LABEL: fcmp_oeq_v16f16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.h, vl16
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; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]
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; CHECK-NEXT: ld1h { z1.h }, p0/z, [x1]
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; CHECK-NEXT: fcmeq p1.h, p0/z, z0.h, z1.h
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; CHECK-NEXT: mov z0.h, p1/z, #-1 // =0xffffffffffffffff
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; CHECK-NEXT: st1h { z0.h }, p0, [x2]
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; CHECK-NEXT: ret
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%op1 = load <16 x half>, ptr %a
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%op2 = load <16 x half>, ptr %b
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%cmp = fcmp oeq <16 x half> %op1, %op2
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%sext = sext <16 x i1> %cmp to <16 x i16>
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store <16 x i16> %sext, ptr %c
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ret void
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}
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define void @fcmp_oeq_v32f16(ptr %a, ptr %b, ptr %c) #0 {
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; VBITS_GE_256-LABEL: fcmp_oeq_v32f16:
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; VBITS_GE_256: // %bb.0:
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; VBITS_GE_256-NEXT: ptrue p0.h, vl16
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; VBITS_GE_256-NEXT: mov x8, #16 // =0x10
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; VBITS_GE_256-NEXT: ld1h { z0.h }, p0/z, [x0, x8, lsl #1]
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; VBITS_GE_256-NEXT: ld1h { z1.h }, p0/z, [x1, x8, lsl #1]
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; VBITS_GE_256-NEXT: ld1h { z2.h }, p0/z, [x0]
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; VBITS_GE_256-NEXT: ld1h { z3.h }, p0/z, [x1]
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; VBITS_GE_256-NEXT: fcmeq p1.h, p0/z, z0.h, z1.h
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; VBITS_GE_256-NEXT: fcmeq p2.h, p0/z, z2.h, z3.h
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; VBITS_GE_256-NEXT: mov z0.h, p1/z, #-1 // =0xffffffffffffffff
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; VBITS_GE_256-NEXT: mov z1.h, p2/z, #-1 // =0xffffffffffffffff
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; VBITS_GE_256-NEXT: st1h { z0.h }, p0, [x2, x8, lsl #1]
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; VBITS_GE_256-NEXT: st1h { z1.h }, p0, [x2]
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; VBITS_GE_256-NEXT: ret
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;
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; VBITS_GE_512-LABEL: fcmp_oeq_v32f16:
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; VBITS_GE_512: // %bb.0:
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; VBITS_GE_512-NEXT: ptrue p0.h, vl32
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; VBITS_GE_512-NEXT: ld1h { z0.h }, p0/z, [x0]
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; VBITS_GE_512-NEXT: ld1h { z1.h }, p0/z, [x1]
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; VBITS_GE_512-NEXT: fcmeq p1.h, p0/z, z0.h, z1.h
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; VBITS_GE_512-NEXT: mov z0.h, p1/z, #-1 // =0xffffffffffffffff
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; VBITS_GE_512-NEXT: st1h { z0.h }, p0, [x2]
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; VBITS_GE_512-NEXT: ret
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%op1 = load <32 x half>, ptr %a
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%op2 = load <32 x half>, ptr %b
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%cmp = fcmp oeq <32 x half> %op1, %op2
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%sext = sext <32 x i1> %cmp to <32 x i16>
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store <32 x i16> %sext, ptr %c
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ret void
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}
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define void @fcmp_oeq_v64f16(ptr %a, ptr %b, ptr %c) vscale_range(8,0) #0 {
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; CHECK-LABEL: fcmp_oeq_v64f16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.h, vl64
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; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]
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; CHECK-NEXT: ld1h { z1.h }, p0/z, [x1]
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; CHECK-NEXT: fcmeq p1.h, p0/z, z0.h, z1.h
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; CHECK-NEXT: mov z0.h, p1/z, #-1 // =0xffffffffffffffff
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; CHECK-NEXT: st1h { z0.h }, p0, [x2]
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; CHECK-NEXT: ret
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%op1 = load <64 x half>, ptr %a
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%op2 = load <64 x half>, ptr %b
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%cmp = fcmp oeq <64 x half> %op1, %op2
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%sext = sext <64 x i1> %cmp to <64 x i16>
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store <64 x i16> %sext, ptr %c
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ret void
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}
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define void @fcmp_oeq_v128f16(ptr %a, ptr %b, ptr %c) vscale_range(16,0) #0 {
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; CHECK-LABEL: fcmp_oeq_v128f16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.h, vl128
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; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]
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; CHECK-NEXT: ld1h { z1.h }, p0/z, [x1]
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; CHECK-NEXT: fcmeq p1.h, p0/z, z0.h, z1.h
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; CHECK-NEXT: mov z0.h, p1/z, #-1 // =0xffffffffffffffff
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; CHECK-NEXT: st1h { z0.h }, p0, [x2]
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; CHECK-NEXT: ret
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%op1 = load <128 x half>, ptr %a
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%op2 = load <128 x half>, ptr %b
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%cmp = fcmp oeq <128 x half> %op1, %op2
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%sext = sext <128 x i1> %cmp to <128 x i16>
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store <128 x i16> %sext, ptr %c
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ret void
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}
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; Don't use SVE for 64-bit vectors.
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define <2 x i32> @fcmp_oeq_v2f32(<2 x float> %op1, <2 x float> %op2) vscale_range(2,0) #0 {
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; CHECK-LABEL: fcmp_oeq_v2f32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: fcmeq v0.2s, v0.2s, v1.2s
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; CHECK-NEXT: ret
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%cmp = fcmp oeq <2 x float> %op1, %op2
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%sext = sext <2 x i1> %cmp to <2 x i32>
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ret <2 x i32> %sext
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}
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; Don't use SVE for 128-bit vectors.
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define <4 x i32> @fcmp_oeq_v4f32(<4 x float> %op1, <4 x float> %op2) vscale_range(2,0) #0 {
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; CHECK-LABEL: fcmp_oeq_v4f32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: fcmeq v0.4s, v0.4s, v1.4s
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; CHECK-NEXT: ret
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%cmp = fcmp oeq <4 x float> %op1, %op2
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%sext = sext <4 x i1> %cmp to <4 x i32>
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ret <4 x i32> %sext
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}
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define void @fcmp_oeq_v8f32(ptr %a, ptr %b, ptr %c) vscale_range(2,0) #0 {
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; CHECK-LABEL: fcmp_oeq_v8f32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.s, vl8
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; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]
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; CHECK-NEXT: ld1w { z1.s }, p0/z, [x1]
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; CHECK-NEXT: fcmeq p1.s, p0/z, z0.s, z1.s
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; CHECK-NEXT: mov z0.s, p1/z, #-1 // =0xffffffffffffffff
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; CHECK-NEXT: st1w { z0.s }, p0, [x2]
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; CHECK-NEXT: ret
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%op1 = load <8 x float>, ptr %a
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%op2 = load <8 x float>, ptr %b
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%cmp = fcmp oeq <8 x float> %op1, %op2
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%sext = sext <8 x i1> %cmp to <8 x i32>
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store <8 x i32> %sext, ptr %c
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ret void
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}
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define void @fcmp_oeq_v16f32(ptr %a, ptr %b, ptr %c) #0 {
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; VBITS_GE_256-LABEL: fcmp_oeq_v16f32:
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; VBITS_GE_256: // %bb.0:
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; VBITS_GE_256-NEXT: ptrue p0.s, vl8
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; VBITS_GE_256-NEXT: mov x8, #8 // =0x8
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; VBITS_GE_256-NEXT: ld1w { z0.s }, p0/z, [x0, x8, lsl #2]
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; VBITS_GE_256-NEXT: ld1w { z1.s }, p0/z, [x1, x8, lsl #2]
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; VBITS_GE_256-NEXT: ld1w { z2.s }, p0/z, [x0]
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; VBITS_GE_256-NEXT: ld1w { z3.s }, p0/z, [x1]
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; VBITS_GE_256-NEXT: fcmeq p1.s, p0/z, z0.s, z1.s
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; VBITS_GE_256-NEXT: fcmeq p2.s, p0/z, z2.s, z3.s
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; VBITS_GE_256-NEXT: mov z0.s, p1/z, #-1 // =0xffffffffffffffff
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; VBITS_GE_256-NEXT: mov z1.s, p2/z, #-1 // =0xffffffffffffffff
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; VBITS_GE_256-NEXT: st1w { z0.s }, p0, [x2, x8, lsl #2]
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; VBITS_GE_256-NEXT: st1w { z1.s }, p0, [x2]
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; VBITS_GE_256-NEXT: ret
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;
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; VBITS_GE_512-LABEL: fcmp_oeq_v16f32:
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; VBITS_GE_512: // %bb.0:
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; VBITS_GE_512-NEXT: ptrue p0.s, vl16
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; VBITS_GE_512-NEXT: ld1w { z0.s }, p0/z, [x0]
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; VBITS_GE_512-NEXT: ld1w { z1.s }, p0/z, [x1]
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; VBITS_GE_512-NEXT: fcmeq p1.s, p0/z, z0.s, z1.s
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; VBITS_GE_512-NEXT: mov z0.s, p1/z, #-1 // =0xffffffffffffffff
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; VBITS_GE_512-NEXT: st1w { z0.s }, p0, [x2]
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; VBITS_GE_512-NEXT: ret
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%op1 = load <16 x float>, ptr %a
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%op2 = load <16 x float>, ptr %b
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%cmp = fcmp oeq <16 x float> %op1, %op2
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%sext = sext <16 x i1> %cmp to <16 x i32>
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store <16 x i32> %sext, ptr %c
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ret void
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}
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define void @fcmp_oeq_v32f32(ptr %a, ptr %b, ptr %c) vscale_range(8,0) #0 {
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; CHECK-LABEL: fcmp_oeq_v32f32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.s, vl32
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; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]
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; CHECK-NEXT: ld1w { z1.s }, p0/z, [x1]
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; CHECK-NEXT: fcmeq p1.s, p0/z, z0.s, z1.s
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; CHECK-NEXT: mov z0.s, p1/z, #-1 // =0xffffffffffffffff
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; CHECK-NEXT: st1w { z0.s }, p0, [x2]
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; CHECK-NEXT: ret
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%op1 = load <32 x float>, ptr %a
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%op2 = load <32 x float>, ptr %b
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%cmp = fcmp oeq <32 x float> %op1, %op2
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%sext = sext <32 x i1> %cmp to <32 x i32>
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store <32 x i32> %sext, ptr %c
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ret void
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}
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define void @fcmp_oeq_v64f32(ptr %a, ptr %b, ptr %c) vscale_range(16,0) #0 {
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; CHECK-LABEL: fcmp_oeq_v64f32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.s, vl64
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; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0]
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; CHECK-NEXT: ld1w { z1.s }, p0/z, [x1]
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; CHECK-NEXT: fcmeq p1.s, p0/z, z0.s, z1.s
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; CHECK-NEXT: mov z0.s, p1/z, #-1 // =0xffffffffffffffff
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; CHECK-NEXT: st1w { z0.s }, p0, [x2]
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; CHECK-NEXT: ret
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%op1 = load <64 x float>, ptr %a
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%op2 = load <64 x float>, ptr %b
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%cmp = fcmp oeq <64 x float> %op1, %op2
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%sext = sext <64 x i1> %cmp to <64 x i32>
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store <64 x i32> %sext, ptr %c
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ret void
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}
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; Don't use SVE for 64-bit vectors.
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define <1 x i64> @fcmp_oeq_v1f64(<1 x double> %op1, <1 x double> %op2) vscale_range(2,0) #0 {
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; CHECK-LABEL: fcmp_oeq_v1f64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: fcmeq d0, d0, d1
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; CHECK-NEXT: ret
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%cmp = fcmp oeq <1 x double> %op1, %op2
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%sext = sext <1 x i1> %cmp to <1 x i64>
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ret <1 x i64> %sext
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}
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; Don't use SVE for 128-bit vectors.
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define <2 x i64> @fcmp_oeq_v2f64(<2 x double> %op1, <2 x double> %op2) vscale_range(2,0) #0 {
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; CHECK-LABEL: fcmp_oeq_v2f64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: fcmeq v0.2d, v0.2d, v1.2d
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; CHECK-NEXT: ret
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%cmp = fcmp oeq <2 x double> %op1, %op2
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%sext = sext <2 x i1> %cmp to <2 x i64>
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ret <2 x i64> %sext
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}
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define void @fcmp_oeq_v4f64(ptr %a, ptr %b, ptr %c) vscale_range(2,0) #0 {
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; CHECK-LABEL: fcmp_oeq_v4f64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.d, vl4
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; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]
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; CHECK-NEXT: ld1d { z1.d }, p0/z, [x1]
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; CHECK-NEXT: fcmeq p1.d, p0/z, z0.d, z1.d
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; CHECK-NEXT: mov z0.d, p1/z, #-1 // =0xffffffffffffffff
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; CHECK-NEXT: st1d { z0.d }, p0, [x2]
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; CHECK-NEXT: ret
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%op1 = load <4 x double>, ptr %a
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%op2 = load <4 x double>, ptr %b
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%cmp = fcmp oeq <4 x double> %op1, %op2
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%sext = sext <4 x i1> %cmp to <4 x i64>
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store <4 x i64> %sext, ptr %c
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ret void
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}
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define void @fcmp_oeq_v8f64(ptr %a, ptr %b, ptr %c) #0 {
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; VBITS_GE_256-LABEL: fcmp_oeq_v8f64:
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; VBITS_GE_256: // %bb.0:
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; VBITS_GE_256-NEXT: ptrue p0.d, vl4
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; VBITS_GE_256-NEXT: mov x8, #4 // =0x4
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; VBITS_GE_256-NEXT: ld1d { z0.d }, p0/z, [x0, x8, lsl #3]
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; VBITS_GE_256-NEXT: ld1d { z1.d }, p0/z, [x1, x8, lsl #3]
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; VBITS_GE_256-NEXT: ld1d { z2.d }, p0/z, [x0]
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; VBITS_GE_256-NEXT: ld1d { z3.d }, p0/z, [x1]
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; VBITS_GE_256-NEXT: fcmeq p1.d, p0/z, z0.d, z1.d
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; VBITS_GE_256-NEXT: fcmeq p2.d, p0/z, z2.d, z3.d
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; VBITS_GE_256-NEXT: mov z0.d, p1/z, #-1 // =0xffffffffffffffff
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; VBITS_GE_256-NEXT: mov z1.d, p2/z, #-1 // =0xffffffffffffffff
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; VBITS_GE_256-NEXT: st1d { z0.d }, p0, [x2, x8, lsl #3]
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; VBITS_GE_256-NEXT: st1d { z1.d }, p0, [x2]
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; VBITS_GE_256-NEXT: ret
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;
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; VBITS_GE_512-LABEL: fcmp_oeq_v8f64:
|
|
; VBITS_GE_512: // %bb.0:
|
|
; VBITS_GE_512-NEXT: ptrue p0.d, vl8
|
|
; VBITS_GE_512-NEXT: ld1d { z0.d }, p0/z, [x0]
|
|
; VBITS_GE_512-NEXT: ld1d { z1.d }, p0/z, [x1]
|
|
; VBITS_GE_512-NEXT: fcmeq p1.d, p0/z, z0.d, z1.d
|
|
; VBITS_GE_512-NEXT: mov z0.d, p1/z, #-1 // =0xffffffffffffffff
|
|
; VBITS_GE_512-NEXT: st1d { z0.d }, p0, [x2]
|
|
; VBITS_GE_512-NEXT: ret
|
|
%op1 = load <8 x double>, ptr %a
|
|
%op2 = load <8 x double>, ptr %b
|
|
%cmp = fcmp oeq <8 x double> %op1, %op2
|
|
%sext = sext <8 x i1> %cmp to <8 x i64>
|
|
store <8 x i64> %sext, ptr %c
|
|
ret void
|
|
}
|
|
|
|
define void @fcmp_oeq_v16f64(ptr %a, ptr %b, ptr %c) vscale_range(8,0) #0 {
|
|
; CHECK-LABEL: fcmp_oeq_v16f64:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: ptrue p0.d, vl16
|
|
; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]
|
|
; CHECK-NEXT: ld1d { z1.d }, p0/z, [x1]
|
|
; CHECK-NEXT: fcmeq p1.d, p0/z, z0.d, z1.d
|
|
; CHECK-NEXT: mov z0.d, p1/z, #-1 // =0xffffffffffffffff
|
|
; CHECK-NEXT: st1d { z0.d }, p0, [x2]
|
|
; CHECK-NEXT: ret
|
|
%op1 = load <16 x double>, ptr %a
|
|
%op2 = load <16 x double>, ptr %b
|
|
%cmp = fcmp oeq <16 x double> %op1, %op2
|
|
%sext = sext <16 x i1> %cmp to <16 x i64>
|
|
store <16 x i64> %sext, ptr %c
|
|
ret void
|
|
}
|
|
|
|
define void @fcmp_oeq_v32f64(ptr %a, ptr %b, ptr %c) vscale_range(16,0) #0 {
|
|
; CHECK-LABEL: fcmp_oeq_v32f64:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: ptrue p0.d, vl32
|
|
; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]
|
|
; CHECK-NEXT: ld1d { z1.d }, p0/z, [x1]
|
|
; CHECK-NEXT: fcmeq p1.d, p0/z, z0.d, z1.d
|
|
; CHECK-NEXT: mov z0.d, p1/z, #-1 // =0xffffffffffffffff
|
|
; CHECK-NEXT: st1d { z0.d }, p0, [x2]
|
|
; CHECK-NEXT: ret
|
|
%op1 = load <32 x double>, ptr %a
|
|
%op2 = load <32 x double>, ptr %b
|
|
%cmp = fcmp oeq <32 x double> %op1, %op2
|
|
%sext = sext <32 x i1> %cmp to <32 x i64>
|
|
store <32 x i64> %sext, ptr %c
|
|
ret void
|
|
}
|
|
|
|
define <4 x i16> @fcmp_oeq_v4bf16(<4 x bfloat> %op1, <4 x bfloat> %op2) vscale_range(2,0) #0 {
|
|
; CHECK-LABEL: fcmp_oeq_v4bf16:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: shll v1.4s, v1.4h, #16
|
|
; CHECK-NEXT: shll v0.4s, v0.4h, #16
|
|
; CHECK-NEXT: fcmeq v0.4s, v0.4s, v1.4s
|
|
; CHECK-NEXT: xtn v0.4h, v0.4s
|
|
; CHECK-NEXT: ret
|
|
%cmp = fcmp oeq <4 x bfloat> %op1, %op2
|
|
%sext = sext <4 x i1> %cmp to <4 x i16>
|
|
ret <4 x i16> %sext
|
|
}
|
|
|
|
define <8 x i16> @fcmp_oeq_v8bf16(<8 x bfloat> %op1, <8 x bfloat> %op2) vscale_range(2,0) #0 {
|
|
; CHECK-LABEL: fcmp_oeq_v8bf16:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1
|
|
; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
|
|
; CHECK-NEXT: ptrue p0.s, vl8
|
|
; CHECK-NEXT: uunpklo z1.s, z1.h
|
|
; CHECK-NEXT: uunpklo z0.s, z0.h
|
|
; CHECK-NEXT: lsl z1.s, z1.s, #16
|
|
; CHECK-NEXT: lsl z0.s, z0.s, #16
|
|
; CHECK-NEXT: fcmeq p0.s, p0/z, z0.s, z1.s
|
|
; CHECK-NEXT: mov z0.s, p0/z, #-1 // =0xffffffffffffffff
|
|
; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h
|
|
; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
|
|
; CHECK-NEXT: ret
|
|
%cmp = fcmp oeq <8 x bfloat> %op1, %op2
|
|
%sext = sext <8 x i1> %cmp to <8 x i16>
|
|
ret <8 x i16> %sext
|
|
}
|
|
|
|
define void @fcmp_oeq_v16bf16(ptr %a, ptr %b, ptr %c) vscale_range(2,0) #0 {
|
|
; CHECK-LABEL: fcmp_oeq_v16bf16:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: ldp q3, q0, [x1]
|
|
; CHECK-NEXT: ptrue p0.s, vl8
|
|
; CHECK-NEXT: ldp q2, q1, [x0]
|
|
; CHECK-NEXT: uunpklo z0.s, z0.h
|
|
; CHECK-NEXT: uunpklo z3.s, z3.h
|
|
; CHECK-NEXT: uunpklo z1.s, z1.h
|
|
; CHECK-NEXT: uunpklo z2.s, z2.h
|
|
; CHECK-NEXT: lsl z0.s, z0.s, #16
|
|
; CHECK-NEXT: lsl z3.s, z3.s, #16
|
|
; CHECK-NEXT: lsl z1.s, z1.s, #16
|
|
; CHECK-NEXT: lsl z2.s, z2.s, #16
|
|
; CHECK-NEXT: fcmeq p1.s, p0/z, z1.s, z0.s
|
|
; CHECK-NEXT: fcmeq p0.s, p0/z, z2.s, z3.s
|
|
; CHECK-NEXT: mov z0.s, p1/z, #-1 // =0xffffffffffffffff
|
|
; CHECK-NEXT: mov z1.s, p0/z, #-1 // =0xffffffffffffffff
|
|
; CHECK-NEXT: ptrue p0.h, vl8
|
|
; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h
|
|
; CHECK-NEXT: uzp1 z1.h, z1.h, z1.h
|
|
; CHECK-NEXT: splice z1.h, p0, z1.h, z0.h
|
|
; CHECK-NEXT: ptrue p0.h, vl16
|
|
; CHECK-NEXT: st1h { z1.h }, p0, [x2]
|
|
; CHECK-NEXT: ret
|
|
%op1 = load <16 x bfloat>, ptr %a
|
|
%op2 = load <16 x bfloat>, ptr %b
|
|
%cmp = fcmp oeq <16 x bfloat> %op1, %op2
|
|
%sext = sext <16 x i1> %cmp to <16 x i16>
|
|
store <16 x i16> %sext, ptr %c
|
|
ret void
|
|
}
|
|
|
|
define void @fcmp_oeq_v32bf16(ptr %a, ptr %b, ptr %c) #0 {
|
|
; VBITS_GE_256-LABEL: fcmp_oeq_v32bf16:
|
|
; VBITS_GE_256: // %bb.0:
|
|
; VBITS_GE_256-NEXT: ldp q0, q1, [x0]
|
|
; VBITS_GE_256-NEXT: ptrue p0.s, vl8
|
|
; VBITS_GE_256-NEXT: ldp q2, q3, [x1]
|
|
; VBITS_GE_256-NEXT: mov x8, #16 // =0x10
|
|
; VBITS_GE_256-NEXT: ldp q4, q5, [x0, #32]
|
|
; VBITS_GE_256-NEXT: ldp q7, q6, [x1, #32]
|
|
; VBITS_GE_256-NEXT: uunpklo z1.s, z1.h
|
|
; VBITS_GE_256-NEXT: uunpklo z3.s, z3.h
|
|
; VBITS_GE_256-NEXT: uunpklo z2.s, z2.h
|
|
; VBITS_GE_256-NEXT: uunpklo z0.s, z0.h
|
|
; VBITS_GE_256-NEXT: uunpklo z5.s, z5.h
|
|
; VBITS_GE_256-NEXT: uunpklo z4.s, z4.h
|
|
; VBITS_GE_256-NEXT: uunpklo z6.s, z6.h
|
|
; VBITS_GE_256-NEXT: uunpklo z7.s, z7.h
|
|
; VBITS_GE_256-NEXT: lsl z1.s, z1.s, #16
|
|
; VBITS_GE_256-NEXT: lsl z3.s, z3.s, #16
|
|
; VBITS_GE_256-NEXT: lsl z2.s, z2.s, #16
|
|
; VBITS_GE_256-NEXT: lsl z0.s, z0.s, #16
|
|
; VBITS_GE_256-NEXT: lsl z5.s, z5.s, #16
|
|
; VBITS_GE_256-NEXT: lsl z4.s, z4.s, #16
|
|
; VBITS_GE_256-NEXT: lsl z6.s, z6.s, #16
|
|
; VBITS_GE_256-NEXT: lsl z7.s, z7.s, #16
|
|
; VBITS_GE_256-NEXT: fcmeq p1.s, p0/z, z1.s, z3.s
|
|
; VBITS_GE_256-NEXT: fcmeq p2.s, p0/z, z5.s, z6.s
|
|
; VBITS_GE_256-NEXT: fcmeq p3.s, p0/z, z4.s, z7.s
|
|
; VBITS_GE_256-NEXT: fcmeq p0.s, p0/z, z0.s, z2.s
|
|
; VBITS_GE_256-NEXT: mov z2.s, p1/z, #-1 // =0xffffffffffffffff
|
|
; VBITS_GE_256-NEXT: mov z0.s, p2/z, #-1 // =0xffffffffffffffff
|
|
; VBITS_GE_256-NEXT: mov z1.s, p3/z, #-1 // =0xffffffffffffffff
|
|
; VBITS_GE_256-NEXT: uzp1 z2.h, z2.h, z2.h
|
|
; VBITS_GE_256-NEXT: mov z3.s, p0/z, #-1 // =0xffffffffffffffff
|
|
; VBITS_GE_256-NEXT: ptrue p0.h, vl8
|
|
; VBITS_GE_256-NEXT: uzp1 z0.h, z0.h, z0.h
|
|
; VBITS_GE_256-NEXT: uzp1 z1.h, z1.h, z1.h
|
|
; VBITS_GE_256-NEXT: uzp1 z3.h, z3.h, z3.h
|
|
; VBITS_GE_256-NEXT: splice z1.h, p0, z1.h, z0.h
|
|
; VBITS_GE_256-NEXT: splice z3.h, p0, z3.h, z2.h
|
|
; VBITS_GE_256-NEXT: ptrue p0.h, vl16
|
|
; VBITS_GE_256-NEXT: st1h { z1.h }, p0, [x2, x8, lsl #1]
|
|
; VBITS_GE_256-NEXT: st1h { z3.h }, p0, [x2]
|
|
; VBITS_GE_256-NEXT: ret
|
|
;
|
|
; VBITS_GE_512-LABEL: fcmp_oeq_v32bf16:
|
|
; VBITS_GE_512: // %bb.0:
|
|
; VBITS_GE_512-NEXT: ldp q0, q1, [x0, #32]
|
|
; VBITS_GE_512-NEXT: ptrue p0.s, vl8
|
|
; VBITS_GE_512-NEXT: ldp q2, q3, [x1, #32]
|
|
; VBITS_GE_512-NEXT: ldp q4, q5, [x1]
|
|
; VBITS_GE_512-NEXT: ldp q6, q7, [x0]
|
|
; VBITS_GE_512-NEXT: uunpklo z1.s, z1.h
|
|
; VBITS_GE_512-NEXT: uunpklo z3.s, z3.h
|
|
; VBITS_GE_512-NEXT: uunpklo z2.s, z2.h
|
|
; VBITS_GE_512-NEXT: uunpklo z0.s, z0.h
|
|
; VBITS_GE_512-NEXT: uunpklo z5.s, z5.h
|
|
; VBITS_GE_512-NEXT: uunpklo z4.s, z4.h
|
|
; VBITS_GE_512-NEXT: uunpklo z7.s, z7.h
|
|
; VBITS_GE_512-NEXT: uunpklo z6.s, z6.h
|
|
; VBITS_GE_512-NEXT: lsl z1.s, z1.s, #16
|
|
; VBITS_GE_512-NEXT: lsl z3.s, z3.s, #16
|
|
; VBITS_GE_512-NEXT: lsl z2.s, z2.s, #16
|
|
; VBITS_GE_512-NEXT: lsl z0.s, z0.s, #16
|
|
; VBITS_GE_512-NEXT: lsl z5.s, z5.s, #16
|
|
; VBITS_GE_512-NEXT: lsl z4.s, z4.s, #16
|
|
; VBITS_GE_512-NEXT: lsl z7.s, z7.s, #16
|
|
; VBITS_GE_512-NEXT: lsl z6.s, z6.s, #16
|
|
; VBITS_GE_512-NEXT: fcmeq p1.s, p0/z, z1.s, z3.s
|
|
; VBITS_GE_512-NEXT: fcmeq p2.s, p0/z, z0.s, z2.s
|
|
; VBITS_GE_512-NEXT: fcmeq p3.s, p0/z, z7.s, z5.s
|
|
; VBITS_GE_512-NEXT: fcmeq p0.s, p0/z, z6.s, z4.s
|
|
; VBITS_GE_512-NEXT: mov z0.s, p1/z, #-1 // =0xffffffffffffffff
|
|
; VBITS_GE_512-NEXT: mov z1.s, p2/z, #-1 // =0xffffffffffffffff
|
|
; VBITS_GE_512-NEXT: mov z2.s, p3/z, #-1 // =0xffffffffffffffff
|
|
; VBITS_GE_512-NEXT: mov z3.s, p0/z, #-1 // =0xffffffffffffffff
|
|
; VBITS_GE_512-NEXT: uzp1 z0.h, z0.h, z0.h
|
|
; VBITS_GE_512-NEXT: ptrue p0.h, vl8
|
|
; VBITS_GE_512-NEXT: uzp1 z1.h, z1.h, z1.h
|
|
; VBITS_GE_512-NEXT: uzp1 z2.h, z2.h, z2.h
|
|
; VBITS_GE_512-NEXT: uzp1 z3.h, z3.h, z3.h
|
|
; VBITS_GE_512-NEXT: splice z1.h, p0, z1.h, z0.h
|
|
; VBITS_GE_512-NEXT: splice z3.h, p0, z3.h, z2.h
|
|
; VBITS_GE_512-NEXT: ptrue p0.h, vl16
|
|
; VBITS_GE_512-NEXT: splice z3.h, p0, z3.h, z1.h
|
|
; VBITS_GE_512-NEXT: ptrue p0.h, vl32
|
|
; VBITS_GE_512-NEXT: st1h { z3.h }, p0, [x2]
|
|
; VBITS_GE_512-NEXT: ret
|
|
%op1 = load <32 x bfloat>, ptr %a
|
|
%op2 = load <32 x bfloat>, ptr %b
|
|
%cmp = fcmp oeq <32 x bfloat> %op1, %op2
|
|
%sext = sext <32 x i1> %cmp to <32 x i16>
|
|
store <32 x i16> %sext, ptr %c
|
|
ret void
|
|
}
|
|
|
|
define void @fcmp_oeq_v64bf16(ptr %a, ptr %b, ptr %c) vscale_range(8,0) #0 {
|
|
; CHECK-LABEL: fcmp_oeq_v64bf16:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: ldp q3, q2, [x1, #96]
|
|
; CHECK-NEXT: ptrue p0.s, vl8
|
|
; CHECK-NEXT: ldp q4, q5, [x0, #96]
|
|
; CHECK-NEXT: ldp q18, q19, [x0, #64]
|
|
; CHECK-NEXT: uunpklo z6.s, z2.h
|
|
; CHECK-NEXT: ldp q2, q17, [x0, #32]
|
|
; CHECK-NEXT: uunpklo z5.s, z5.h
|
|
; CHECK-NEXT: uunpklo z3.s, z3.h
|
|
; CHECK-NEXT: uunpklo z4.s, z4.h
|
|
; CHECK-NEXT: ldp q22, q23, [x1, #32]
|
|
; CHECK-NEXT: uunpklo z19.s, z19.h
|
|
; CHECK-NEXT: ldp q0, q1, [x0]
|
|
; CHECK-NEXT: uunpklo z18.s, z18.h
|
|
; CHECK-NEXT: lsl z6.s, z6.s, #16
|
|
; CHECK-NEXT: ldp q7, q16, [x1, #64]
|
|
; CHECK-NEXT: lsl z5.s, z5.s, #16
|
|
; CHECK-NEXT: ldp q20, q21, [x1]
|
|
; CHECK-NEXT: lsl z3.s, z3.s, #16
|
|
; CHECK-NEXT: lsl z4.s, z4.s, #16
|
|
; CHECK-NEXT: uunpklo z2.s, z2.h
|
|
; CHECK-NEXT: uunpklo z16.s, z16.h
|
|
; CHECK-NEXT: uunpklo z7.s, z7.h
|
|
; CHECK-NEXT: uunpklo z1.s, z1.h
|
|
; CHECK-NEXT: fcmeq p1.s, p0/z, z5.s, z6.s
|
|
; CHECK-NEXT: uunpklo z5.s, z23.h
|
|
; CHECK-NEXT: uunpklo z6.s, z17.h
|
|
; CHECK-NEXT: lsl z17.s, z19.s, #16
|
|
; CHECK-NEXT: uunpklo z19.s, z22.h
|
|
; CHECK-NEXT: uunpklo z21.s, z21.h
|
|
; CHECK-NEXT: uunpklo z20.s, z20.h
|
|
; CHECK-NEXT: uunpklo z0.s, z0.h
|
|
; CHECK-NEXT: lsl z18.s, z18.s, #16
|
|
; CHECK-NEXT: fcmeq p2.s, p0/z, z4.s, z3.s
|
|
; CHECK-NEXT: lsl z16.s, z16.s, #16
|
|
; CHECK-NEXT: lsl z7.s, z7.s, #16
|
|
; CHECK-NEXT: lsl z3.s, z5.s, #16
|
|
; CHECK-NEXT: lsl z4.s, z6.s, #16
|
|
; CHECK-NEXT: lsl z2.s, z2.s, #16
|
|
; CHECK-NEXT: lsl z5.s, z19.s, #16
|
|
; CHECK-NEXT: lsl z6.s, z21.s, #16
|
|
; CHECK-NEXT: lsl z1.s, z1.s, #16
|
|
; CHECK-NEXT: lsl z0.s, z0.s, #16
|
|
; CHECK-NEXT: fcmeq p5.s, p0/z, z4.s, z3.s
|
|
; CHECK-NEXT: lsl z3.s, z20.s, #16
|
|
; CHECK-NEXT: fcmeq p3.s, p0/z, z17.s, z16.s
|
|
; CHECK-NEXT: fcmeq p4.s, p0/z, z18.s, z7.s
|
|
; CHECK-NEXT: fcmeq p6.s, p0/z, z2.s, z5.s
|
|
; CHECK-NEXT: fcmeq p7.s, p0/z, z1.s, z6.s
|
|
; CHECK-NEXT: mov z1.s, p2/z, #-1 // =0xffffffffffffffff
|
|
; CHECK-NEXT: mov z4.s, p5/z, #-1 // =0xffffffffffffffff
|
|
; CHECK-NEXT: mov z2.s, p3/z, #-1 // =0xffffffffffffffff
|
|
; CHECK-NEXT: fcmeq p0.s, p0/z, z0.s, z3.s
|
|
; CHECK-NEXT: mov z0.s, p1/z, #-1 // =0xffffffffffffffff
|
|
; CHECK-NEXT: mov z3.s, p4/z, #-1 // =0xffffffffffffffff
|
|
; CHECK-NEXT: mov z5.s, p6/z, #-1 // =0xffffffffffffffff
|
|
; CHECK-NEXT: uzp1 z1.h, z1.h, z1.h
|
|
; CHECK-NEXT: uzp1 z4.h, z4.h, z4.h
|
|
; CHECK-NEXT: mov z6.s, p7/z, #-1 // =0xffffffffffffffff
|
|
; CHECK-NEXT: uzp1 z2.h, z2.h, z2.h
|
|
; CHECK-NEXT: uzp1 z0.h, z0.h, z0.h
|
|
; CHECK-NEXT: uzp1 z3.h, z3.h, z3.h
|
|
; CHECK-NEXT: mov z7.s, p0/z, #-1 // =0xffffffffffffffff
|
|
; CHECK-NEXT: uzp1 z5.h, z5.h, z5.h
|
|
; CHECK-NEXT: ptrue p0.h, vl8
|
|
; CHECK-NEXT: uzp1 z6.h, z6.h, z6.h
|
|
; CHECK-NEXT: splice z1.h, p0, z1.h, z0.h
|
|
; CHECK-NEXT: splice z3.h, p0, z3.h, z2.h
|
|
; CHECK-NEXT: uzp1 z7.h, z7.h, z7.h
|
|
; CHECK-NEXT: splice z5.h, p0, z5.h, z4.h
|
|
; CHECK-NEXT: splice z7.h, p0, z7.h, z6.h
|
|
; CHECK-NEXT: ptrue p0.h, vl16
|
|
; CHECK-NEXT: splice z3.h, p0, z3.h, z1.h
|
|
; CHECK-NEXT: splice z7.h, p0, z7.h, z5.h
|
|
; CHECK-NEXT: ptrue p0.h, vl32
|
|
; CHECK-NEXT: splice z7.h, p0, z7.h, z3.h
|
|
; CHECK-NEXT: ptrue p0.h, vl64
|
|
; CHECK-NEXT: st1h { z7.h }, p0, [x2]
|
|
; CHECK-NEXT: ret
|
|
%op1 = load <64 x bfloat>, ptr %a
|
|
%op2 = load <64 x bfloat>, ptr %b
|
|
%cmp = fcmp oeq <64 x bfloat> %op1, %op2
|
|
%sext = sext <64 x i1> %cmp to <64 x i16>
|
|
store <64 x i16> %sext, ptr %c
|
|
ret void
|
|
}
|
|
|
|
;
|
|
; FCMP UEQ
|
|
;
|
|
|
|
define void @fcmp_ueq_v16f16(ptr %a, ptr %b, ptr %c) vscale_range(2,0) #0 {
|
|
; CHECK-LABEL: fcmp_ueq_v16f16:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: ptrue p0.h, vl16
|
|
; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]
|
|
; CHECK-NEXT: ld1h { z1.h }, p0/z, [x1]
|
|
; CHECK-NEXT: fcmuo p1.h, p0/z, z0.h, z1.h
|
|
; CHECK-NEXT: fcmeq p2.h, p0/z, z0.h, z1.h
|
|
; CHECK-NEXT: mov p1.b, p2/m, p2.b
|
|
; CHECK-NEXT: mov z0.h, p1/z, #-1 // =0xffffffffffffffff
|
|
; CHECK-NEXT: st1h { z0.h }, p0, [x2]
|
|
; CHECK-NEXT: ret
|
|
%op1 = load <16 x half>, ptr %a
|
|
%op2 = load <16 x half>, ptr %b
|
|
%cmp = fcmp ueq <16 x half> %op1, %op2
|
|
%sext = sext <16 x i1> %cmp to <16 x i16>
|
|
store <16 x i16> %sext, ptr %c
|
|
ret void
|
|
}
|
|
|
|
;
|
|
; FCMP ONE
|
|
;
|
|
|
|
define void @fcmp_one_v16f16(ptr %a, ptr %b, ptr %c) vscale_range(2,0) #0 {
|
|
; CHECK-LABEL: fcmp_one_v16f16:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: ptrue p0.h, vl16
|
|
; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]
|
|
; CHECK-NEXT: ld1h { z1.h }, p0/z, [x1]
|
|
; CHECK-NEXT: fcmgt p1.h, p0/z, z1.h, z0.h
|
|
; CHECK-NEXT: fcmgt p2.h, p0/z, z0.h, z1.h
|
|
; CHECK-NEXT: mov p1.b, p2/m, p2.b
|
|
; CHECK-NEXT: mov z0.h, p1/z, #-1 // =0xffffffffffffffff
|
|
; CHECK-NEXT: st1h { z0.h }, p0, [x2]
|
|
; CHECK-NEXT: ret
|
|
%op1 = load <16 x half>, ptr %a
|
|
%op2 = load <16 x half>, ptr %b
|
|
%cmp = fcmp one <16 x half> %op1, %op2
|
|
%sext = sext <16 x i1> %cmp to <16 x i16>
|
|
store <16 x i16> %sext, ptr %c
|
|
ret void
|
|
}
|
|
|
|
;
|
|
; FCMP UNE
|
|
;
|
|
|
|
define void @fcmp_une_v16f16(ptr %a, ptr %b, ptr %c) vscale_range(2,0) #0 {
|
|
; CHECK-LABEL: fcmp_une_v16f16:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: ptrue p0.h, vl16
|
|
; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]
|
|
; CHECK-NEXT: ld1h { z1.h }, p0/z, [x1]
|
|
; CHECK-NEXT: fcmne p1.h, p0/z, z0.h, z1.h
|
|
; CHECK-NEXT: mov z0.h, p1/z, #-1 // =0xffffffffffffffff
|
|
; CHECK-NEXT: st1h { z0.h }, p0, [x2]
|
|
; CHECK-NEXT: ret
|
|
%op1 = load <16 x half>, ptr %a
|
|
%op2 = load <16 x half>, ptr %b
|
|
%cmp = fcmp une <16 x half> %op1, %op2
|
|
%sext = sext <16 x i1> %cmp to <16 x i16>
|
|
store <16 x i16> %sext, ptr %c
|
|
ret void
|
|
}
|
|
|
|
;
|
|
; FCMP OGT
|
|
;
|
|
|
|
define void @fcmp_ogt_v16f16(ptr %a, ptr %b, ptr %c) vscale_range(2,0) #0 {
|
|
; CHECK-LABEL: fcmp_ogt_v16f16:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: ptrue p0.h, vl16
|
|
; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]
|
|
; CHECK-NEXT: ld1h { z1.h }, p0/z, [x1]
|
|
; CHECK-NEXT: fcmgt p1.h, p0/z, z0.h, z1.h
|
|
; CHECK-NEXT: mov z0.h, p1/z, #-1 // =0xffffffffffffffff
|
|
; CHECK-NEXT: st1h { z0.h }, p0, [x2]
|
|
; CHECK-NEXT: ret
|
|
%op1 = load <16 x half>, ptr %a
|
|
%op2 = load <16 x half>, ptr %b
|
|
%cmp = fcmp ogt <16 x half> %op1, %op2
|
|
%sext = sext <16 x i1> %cmp to <16 x i16>
|
|
store <16 x i16> %sext, ptr %c
|
|
ret void
|
|
}
|
|
|
|
;
|
|
; FCMP UGT
|
|
;
|
|
|
|
define void @fcmp_ugt_v16f16(ptr %a, ptr %b, ptr %c) vscale_range(2,0) #0 {
|
|
; CHECK-LABEL: fcmp_ugt_v16f16:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: ptrue p0.h, vl16
|
|
; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]
|
|
; CHECK-NEXT: ld1h { z1.h }, p0/z, [x1]
|
|
; CHECK-NEXT: fcmge p1.h, p0/z, z1.h, z0.h
|
|
; CHECK-NEXT: mov z0.h, p1/z, #-1 // =0xffffffffffffffff
|
|
; CHECK-NEXT: subr z0.b, z0.b, #255 // =0xff
|
|
; CHECK-NEXT: st1h { z0.h }, p0, [x2]
|
|
; CHECK-NEXT: ret
|
|
%op1 = load <16 x half>, ptr %a
|
|
%op2 = load <16 x half>, ptr %b
|
|
%cmp = fcmp ugt <16 x half> %op1, %op2
|
|
%sext = sext <16 x i1> %cmp to <16 x i16>
|
|
store <16 x i16> %sext, ptr %c
|
|
ret void
|
|
}
|
|
|
|
;
|
|
; FCMP OLT
|
|
;
|
|
|
|
define void @fcmp_olt_v16f16(ptr %a, ptr %b, ptr %c) vscale_range(2,0) #0 {
|
|
; CHECK-LABEL: fcmp_olt_v16f16:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: ptrue p0.h, vl16
|
|
; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]
|
|
; CHECK-NEXT: ld1h { z1.h }, p0/z, [x1]
|
|
; CHECK-NEXT: fcmgt p1.h, p0/z, z1.h, z0.h
|
|
; CHECK-NEXT: mov z0.h, p1/z, #-1 // =0xffffffffffffffff
|
|
; CHECK-NEXT: st1h { z0.h }, p0, [x2]
|
|
; CHECK-NEXT: ret
|
|
%op1 = load <16 x half>, ptr %a
|
|
%op2 = load <16 x half>, ptr %b
|
|
%cmp = fcmp olt <16 x half> %op1, %op2
|
|
%sext = sext <16 x i1> %cmp to <16 x i16>
|
|
store <16 x i16> %sext, ptr %c
|
|
ret void
|
|
}
|
|
|
|
;
|
|
; FCMP ULT
|
|
;
|
|
|
|
define void @fcmp_ult_v16f16(ptr %a, ptr %b, ptr %c) vscale_range(2,0) #0 {
|
|
; CHECK-LABEL: fcmp_ult_v16f16:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: ptrue p0.h, vl16
|
|
; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]
|
|
; CHECK-NEXT: ld1h { z1.h }, p0/z, [x1]
|
|
; CHECK-NEXT: fcmge p1.h, p0/z, z0.h, z1.h
|
|
; CHECK-NEXT: mov z0.h, p1/z, #-1 // =0xffffffffffffffff
|
|
; CHECK-NEXT: subr z0.b, z0.b, #255 // =0xff
|
|
; CHECK-NEXT: st1h { z0.h }, p0, [x2]
|
|
; CHECK-NEXT: ret
|
|
%op1 = load <16 x half>, ptr %a
|
|
%op2 = load <16 x half>, ptr %b
|
|
%cmp = fcmp ult <16 x half> %op1, %op2
|
|
%sext = sext <16 x i1> %cmp to <16 x i16>
|
|
store <16 x i16> %sext, ptr %c
|
|
ret void
|
|
}
|
|
|
|
;
|
|
; FCMP OGE
|
|
;
|
|
|
|
define void @fcmp_oge_v16f16(ptr %a, ptr %b, ptr %c) vscale_range(2,0) #0 {
|
|
; CHECK-LABEL: fcmp_oge_v16f16:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: ptrue p0.h, vl16
|
|
; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]
|
|
; CHECK-NEXT: ld1h { z1.h }, p0/z, [x1]
|
|
; CHECK-NEXT: fcmge p1.h, p0/z, z0.h, z1.h
|
|
; CHECK-NEXT: mov z0.h, p1/z, #-1 // =0xffffffffffffffff
|
|
; CHECK-NEXT: st1h { z0.h }, p0, [x2]
|
|
; CHECK-NEXT: ret
|
|
%op1 = load <16 x half>, ptr %a
|
|
%op2 = load <16 x half>, ptr %b
|
|
%cmp = fcmp oge <16 x half> %op1, %op2
|
|
%sext = sext <16 x i1> %cmp to <16 x i16>
|
|
store <16 x i16> %sext, ptr %c
|
|
ret void
|
|
}
|
|
|
|
;
|
|
; FCMP UGE
|
|
;
|
|
|
|
define void @fcmp_uge_v16f16(ptr %a, ptr %b, ptr %c) vscale_range(2,0) #0 {
|
|
; CHECK-LABEL: fcmp_uge_v16f16:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: ptrue p0.h, vl16
|
|
; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]
|
|
; CHECK-NEXT: ld1h { z1.h }, p0/z, [x1]
|
|
; CHECK-NEXT: fcmgt p1.h, p0/z, z1.h, z0.h
|
|
; CHECK-NEXT: mov z0.h, p1/z, #-1 // =0xffffffffffffffff
|
|
; CHECK-NEXT: subr z0.b, z0.b, #255 // =0xff
|
|
; CHECK-NEXT: st1h { z0.h }, p0, [x2]
|
|
; CHECK-NEXT: ret
|
|
%op1 = load <16 x half>, ptr %a
|
|
%op2 = load <16 x half>, ptr %b
|
|
%cmp = fcmp uge <16 x half> %op1, %op2
|
|
%sext = sext <16 x i1> %cmp to <16 x i16>
|
|
store <16 x i16> %sext, ptr %c
|
|
ret void
|
|
}
|
|
|
|
;
|
|
; FCMP OLE
|
|
;
|
|
|
|
define void @fcmp_ole_v16f16(ptr %a, ptr %b, ptr %c) vscale_range(2,0) #0 {
|
|
; CHECK-LABEL: fcmp_ole_v16f16:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: ptrue p0.h, vl16
|
|
; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]
|
|
; CHECK-NEXT: ld1h { z1.h }, p0/z, [x1]
|
|
; CHECK-NEXT: fcmge p1.h, p0/z, z1.h, z0.h
|
|
; CHECK-NEXT: mov z0.h, p1/z, #-1 // =0xffffffffffffffff
|
|
; CHECK-NEXT: st1h { z0.h }, p0, [x2]
|
|
; CHECK-NEXT: ret
|
|
%op1 = load <16 x half>, ptr %a
|
|
%op2 = load <16 x half>, ptr %b
|
|
%cmp = fcmp ole <16 x half> %op1, %op2
|
|
%sext = sext <16 x i1> %cmp to <16 x i16>
|
|
store <16 x i16> %sext, ptr %c
|
|
ret void
|
|
}
|
|
|
|
;
|
|
; FCMP ULE
|
|
;
|
|
|
|
define void @fcmp_ule_v16f16(ptr %a, ptr %b, ptr %c) vscale_range(2,0) #0 {
|
|
; CHECK-LABEL: fcmp_ule_v16f16:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: ptrue p0.h, vl16
|
|
; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]
|
|
; CHECK-NEXT: ld1h { z1.h }, p0/z, [x1]
|
|
; CHECK-NEXT: fcmgt p1.h, p0/z, z0.h, z1.h
|
|
; CHECK-NEXT: mov z0.h, p1/z, #-1 // =0xffffffffffffffff
|
|
; CHECK-NEXT: subr z0.b, z0.b, #255 // =0xff
|
|
; CHECK-NEXT: st1h { z0.h }, p0, [x2]
|
|
; CHECK-NEXT: ret
|
|
%op1 = load <16 x half>, ptr %a
|
|
%op2 = load <16 x half>, ptr %b
|
|
%cmp = fcmp ule <16 x half> %op1, %op2
|
|
%sext = sext <16 x i1> %cmp to <16 x i16>
|
|
store <16 x i16> %sext, ptr %c
|
|
ret void
|
|
}
|
|
|
|
;
|
|
; FCMP UNO
|
|
;
|
|
|
|
define void @fcmp_uno_v16f16(ptr %a, ptr %b, ptr %c) vscale_range(2,0) #0 {
|
|
; CHECK-LABEL: fcmp_uno_v16f16:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: ptrue p0.h, vl16
|
|
; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]
|
|
; CHECK-NEXT: ld1h { z1.h }, p0/z, [x1]
|
|
; CHECK-NEXT: fcmuo p1.h, p0/z, z0.h, z1.h
|
|
; CHECK-NEXT: mov z0.h, p1/z, #-1 // =0xffffffffffffffff
|
|
; CHECK-NEXT: st1h { z0.h }, p0, [x2]
|
|
; CHECK-NEXT: ret
|
|
%op1 = load <16 x half>, ptr %a
|
|
%op2 = load <16 x half>, ptr %b
|
|
%cmp = fcmp uno <16 x half> %op1, %op2
|
|
%sext = sext <16 x i1> %cmp to <16 x i16>
|
|
store <16 x i16> %sext, ptr %c
|
|
ret void
|
|
}
|
|
|
|
;
|
|
; FCMP ORD
|
|
;
|
|
|
|
define void @fcmp_ord_v16f16(ptr %a, ptr %b, ptr %c) vscale_range(2,0) #0 {
|
|
; CHECK-LABEL: fcmp_ord_v16f16:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: ptrue p0.h, vl16
|
|
; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]
|
|
; CHECK-NEXT: ld1h { z1.h }, p0/z, [x1]
|
|
; CHECK-NEXT: fcmuo p1.h, p0/z, z0.h, z1.h
|
|
; CHECK-NEXT: mov z0.h, p1/z, #-1 // =0xffffffffffffffff
|
|
; CHECK-NEXT: subr z0.b, z0.b, #255 // =0xff
|
|
; CHECK-NEXT: st1h { z0.h }, p0, [x2]
|
|
; CHECK-NEXT: ret
|
|
%op1 = load <16 x half>, ptr %a
|
|
%op2 = load <16 x half>, ptr %b
|
|
%cmp = fcmp ord <16 x half> %op1, %op2
|
|
%sext = sext <16 x i1> %cmp to <16 x i16>
|
|
store <16 x i16> %sext, ptr %c
|
|
ret void
|
|
}
|
|
|
|
;
|
|
; FCMP EQ
|
|
;
|
|
|
|
define void @fcmp_eq_v16f16(ptr %a, ptr %b, ptr %c) vscale_range(2,0) #0 {
|
|
; CHECK-LABEL: fcmp_eq_v16f16:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: ptrue p0.h, vl16
|
|
; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]
|
|
; CHECK-NEXT: ld1h { z1.h }, p0/z, [x1]
|
|
; CHECK-NEXT: fcmeq p1.h, p0/z, z0.h, z1.h
|
|
; CHECK-NEXT: mov z0.h, p1/z, #-1 // =0xffffffffffffffff
|
|
; CHECK-NEXT: st1h { z0.h }, p0, [x2]
|
|
; CHECK-NEXT: ret
|
|
%op1 = load <16 x half>, ptr %a
|
|
%op2 = load <16 x half>, ptr %b
|
|
%cmp = fcmp fast oeq <16 x half> %op1, %op2
|
|
%sext = sext <16 x i1> %cmp to <16 x i16>
|
|
store <16 x i16> %sext, ptr %c
|
|
ret void
|
|
}
|
|
|
|
;
|
|
; FCMP NE
|
|
;
|
|
|
|
define void @fcmp_ne_v16f16(ptr %a, ptr %b, ptr %c) vscale_range(2,0) #0 {
|
|
; CHECK-LABEL: fcmp_ne_v16f16:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: ptrue p0.h, vl16
|
|
; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]
|
|
; CHECK-NEXT: ld1h { z1.h }, p0/z, [x1]
|
|
; CHECK-NEXT: fcmne p1.h, p0/z, z0.h, z1.h
|
|
; CHECK-NEXT: mov z0.h, p1/z, #-1 // =0xffffffffffffffff
|
|
; CHECK-NEXT: st1h { z0.h }, p0, [x2]
|
|
; CHECK-NEXT: ret
|
|
%op1 = load <16 x half>, ptr %a
|
|
%op2 = load <16 x half>, ptr %b
|
|
%cmp = fcmp fast one <16 x half> %op1, %op2
|
|
%sext = sext <16 x i1> %cmp to <16 x i16>
|
|
store <16 x i16> %sext, ptr %c
|
|
ret void
|
|
}
|
|
|
|
;
|
|
; FCMP GT
|
|
;
|
|
|
|
define void @fcmp_gt_v16f16(ptr %a, ptr %b, ptr %c) vscale_range(2,0) #0 {
|
|
; CHECK-LABEL: fcmp_gt_v16f16:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: ptrue p0.h, vl16
|
|
; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]
|
|
; CHECK-NEXT: ld1h { z1.h }, p0/z, [x1]
|
|
; CHECK-NEXT: fcmgt p1.h, p0/z, z0.h, z1.h
|
|
; CHECK-NEXT: mov z0.h, p1/z, #-1 // =0xffffffffffffffff
|
|
; CHECK-NEXT: st1h { z0.h }, p0, [x2]
|
|
; CHECK-NEXT: ret
|
|
%op1 = load <16 x half>, ptr %a
|
|
%op2 = load <16 x half>, ptr %b
|
|
%cmp = fcmp fast ogt <16 x half> %op1, %op2
|
|
%sext = sext <16 x i1> %cmp to <16 x i16>
|
|
store <16 x i16> %sext, ptr %c
|
|
ret void
|
|
}
|
|
|
|
;
|
|
; FCMP LT
|
|
;
|
|
|
|
define void @fcmp_lt_v16f16(ptr %a, ptr %b, ptr %c) vscale_range(2,0) #0 {
|
|
; CHECK-LABEL: fcmp_lt_v16f16:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: ptrue p0.h, vl16
|
|
; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]
|
|
; CHECK-NEXT: ld1h { z1.h }, p0/z, [x1]
|
|
; CHECK-NEXT: fcmgt p1.h, p0/z, z1.h, z0.h
|
|
; CHECK-NEXT: mov z0.h, p1/z, #-1 // =0xffffffffffffffff
|
|
; CHECK-NEXT: st1h { z0.h }, p0, [x2]
|
|
; CHECK-NEXT: ret
|
|
%op1 = load <16 x half>, ptr %a
|
|
%op2 = load <16 x half>, ptr %b
|
|
%cmp = fcmp fast olt <16 x half> %op1, %op2
|
|
%sext = sext <16 x i1> %cmp to <16 x i16>
|
|
store <16 x i16> %sext, ptr %c
|
|
ret void
|
|
}
|
|
|
|
;
|
|
; FCMP GE
|
|
;
|
|
|
|
define void @fcmp_ge_v16f16(ptr %a, ptr %b, ptr %c) vscale_range(2,0) #0 {
|
|
; CHECK-LABEL: fcmp_ge_v16f16:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: ptrue p0.h, vl16
|
|
; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]
|
|
; CHECK-NEXT: ld1h { z1.h }, p0/z, [x1]
|
|
; CHECK-NEXT: fcmge p1.h, p0/z, z0.h, z1.h
|
|
; CHECK-NEXT: mov z0.h, p1/z, #-1 // =0xffffffffffffffff
|
|
; CHECK-NEXT: st1h { z0.h }, p0, [x2]
|
|
; CHECK-NEXT: ret
|
|
%op1 = load <16 x half>, ptr %a
|
|
%op2 = load <16 x half>, ptr %b
|
|
%cmp = fcmp fast oge <16 x half> %op1, %op2
|
|
%sext = sext <16 x i1> %cmp to <16 x i16>
|
|
store <16 x i16> %sext, ptr %c
|
|
ret void
|
|
}
|
|
|
|
;
|
|
; FCMP LE
|
|
;
|
|
|
|
define void @fcmp_le_v16f16(ptr %a, ptr %b, ptr %c) vscale_range(2,0) #0 {
|
|
; CHECK-LABEL: fcmp_le_v16f16:
|
|
; CHECK: // %bb.0:
|
|
; CHECK-NEXT: ptrue p0.h, vl16
|
|
; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]
|
|
; CHECK-NEXT: ld1h { z1.h }, p0/z, [x1]
|
|
; CHECK-NEXT: fcmge p1.h, p0/z, z1.h, z0.h
|
|
; CHECK-NEXT: mov z0.h, p1/z, #-1 // =0xffffffffffffffff
|
|
; CHECK-NEXT: st1h { z0.h }, p0, [x2]
|
|
; CHECK-NEXT: ret
|
|
%op1 = load <16 x half>, ptr %a
|
|
%op2 = load <16 x half>, ptr %b
|
|
%cmp = fcmp fast ole <16 x half> %op1, %op2
|
|
%sext = sext <16 x i1> %cmp to <16 x i16>
|
|
store <16 x i16> %sext, ptr %c
|
|
ret void
|
|
}
|
|
|
|
attributes #0 = { "target-features"="+sve" }
|