derek.holloway
7502bf64a4
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232 lines
8.0 KiB
LLVM
232 lines
8.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -aarch64-sve-vector-bits-min=256 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_256
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; RUN: llc -aarch64-sve-vector-bits-min=512 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_512
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; RUN: llc -aarch64-sve-vector-bits-min=2048 < %s | FileCheck %s -check-prefixes=CHECK,VBITS_GE_512
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target triple = "aarch64-unknown-linux-gnu"
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define void @store_trunc_v2i64i8(ptr %ap, ptr %dest) vscale_range(2,0) #0 {
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; CHECK-LABEL: store_trunc_v2i64i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.d, vl2
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; CHECK-NEXT: ldr q0, [x0]
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; CHECK-NEXT: st1b { z0.d }, p0, [x1]
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; CHECK-NEXT: ret
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%a = load <2 x i64>, ptr %ap
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%val = trunc <2 x i64> %a to <2 x i8>
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store <2 x i8> %val, ptr %dest
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ret void
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}
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define void @store_trunc_v4i64i8(ptr %ap, ptr %dest) vscale_range(2,0) #0 {
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; CHECK-LABEL: store_trunc_v4i64i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.d, vl4
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; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]
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; CHECK-NEXT: st1b { z0.d }, p0, [x1]
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; CHECK-NEXT: ret
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%a = load <4 x i64>, ptr %ap
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%val = trunc <4 x i64> %a to <4 x i8>
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store <4 x i8> %val, ptr %dest
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ret void
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}
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define void @store_trunc_v8i64i8(ptr %ap, ptr %dest) #0 {
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; VBITS_GE_256-LABEL: store_trunc_v8i64i8:
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; VBITS_GE_256: // %bb.0:
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; VBITS_GE_256-NEXT: ptrue p0.d, vl4
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; VBITS_GE_256-NEXT: mov x8, #4 // =0x4
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; VBITS_GE_256-NEXT: ld1d { z0.d }, p0/z, [x0, x8, lsl #3]
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; VBITS_GE_256-NEXT: ld1d { z1.d }, p0/z, [x0]
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; VBITS_GE_256-NEXT: ptrue p0.s, vl4
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; VBITS_GE_256-NEXT: uzp1 z0.s, z0.s, z0.s
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; VBITS_GE_256-NEXT: uzp1 z1.s, z1.s, z1.s
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; VBITS_GE_256-NEXT: splice z1.s, p0, z1.s, z0.s
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; VBITS_GE_256-NEXT: ptrue p0.s, vl8
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; VBITS_GE_256-NEXT: st1b { z1.s }, p0, [x1]
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; VBITS_GE_256-NEXT: ret
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;
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; VBITS_GE_512-LABEL: store_trunc_v8i64i8:
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; VBITS_GE_512: // %bb.0:
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; VBITS_GE_512-NEXT: ptrue p0.d, vl8
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; VBITS_GE_512-NEXT: ld1d { z0.d }, p0/z, [x0]
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; VBITS_GE_512-NEXT: st1b { z0.d }, p0, [x1]
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; VBITS_GE_512-NEXT: ret
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%a = load <8 x i64>, ptr %ap
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%val = trunc <8 x i64> %a to <8 x i8>
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store <8 x i8> %val, ptr %dest
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ret void
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}
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define void @store_trunc_v16i64i8(ptr %ap, ptr %dest) vscale_range(8,0) #0 {
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; CHECK-LABEL: store_trunc_v16i64i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.d, vl16
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; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]
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; CHECK-NEXT: st1b { z0.d }, p0, [x1]
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; CHECK-NEXT: ret
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%a = load <16 x i64>, ptr %ap
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%val = trunc <16 x i64> %a to <16 x i8>
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store <16 x i8> %val, ptr %dest
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ret void
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}
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define void @store_trunc_v32i64i8(ptr %ap, ptr %dest) vscale_range(16,0) #0 {
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; CHECK-LABEL: store_trunc_v32i64i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.d, vl32
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; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]
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; CHECK-NEXT: st1b { z0.d }, p0, [x1]
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; CHECK-NEXT: ret
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%a = load <32 x i64>, ptr %ap
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%val = trunc <32 x i64> %a to <32 x i8>
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store <32 x i8> %val, ptr %dest
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ret void
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}
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define void @store_trunc_v8i64i16(ptr %ap, ptr %dest) #0 {
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; VBITS_GE_256-LABEL: store_trunc_v8i64i16:
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; VBITS_GE_256: // %bb.0:
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; VBITS_GE_256-NEXT: ptrue p0.d, vl4
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; VBITS_GE_256-NEXT: mov x8, #4 // =0x4
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; VBITS_GE_256-NEXT: ld1d { z0.d }, p0/z, [x0, x8, lsl #3]
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; VBITS_GE_256-NEXT: ld1d { z1.d }, p0/z, [x0]
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; VBITS_GE_256-NEXT: st1h { z0.d }, p0, [x1, x8, lsl #1]
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; VBITS_GE_256-NEXT: st1h { z1.d }, p0, [x1]
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; VBITS_GE_256-NEXT: ret
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;
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; VBITS_GE_512-LABEL: store_trunc_v8i64i16:
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; VBITS_GE_512: // %bb.0:
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; VBITS_GE_512-NEXT: ptrue p0.d, vl8
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; VBITS_GE_512-NEXT: ld1d { z0.d }, p0/z, [x0]
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; VBITS_GE_512-NEXT: st1h { z0.d }, p0, [x1]
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; VBITS_GE_512-NEXT: ret
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%a = load <8 x i64>, ptr %ap
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%val = trunc <8 x i64> %a to <8 x i16>
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store <8 x i16> %val, ptr %dest
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ret void
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}
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define void @store_trunc_v8i64i32(ptr %ap, ptr %dest) #0 {
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; VBITS_GE_256-LABEL: store_trunc_v8i64i32:
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; VBITS_GE_256: // %bb.0:
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; VBITS_GE_256-NEXT: ptrue p0.d, vl4
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; VBITS_GE_256-NEXT: mov x8, #4 // =0x4
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; VBITS_GE_256-NEXT: ld1d { z0.d }, p0/z, [x0, x8, lsl #3]
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; VBITS_GE_256-NEXT: ld1d { z1.d }, p0/z, [x0]
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; VBITS_GE_256-NEXT: st1w { z0.d }, p0, [x1, x8, lsl #2]
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; VBITS_GE_256-NEXT: st1w { z1.d }, p0, [x1]
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; VBITS_GE_256-NEXT: ret
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;
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; VBITS_GE_512-LABEL: store_trunc_v8i64i32:
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; VBITS_GE_512: // %bb.0:
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; VBITS_GE_512-NEXT: ptrue p0.d, vl8
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; VBITS_GE_512-NEXT: ld1d { z0.d }, p0/z, [x0]
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; VBITS_GE_512-NEXT: st1w { z0.d }, p0, [x1]
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; VBITS_GE_512-NEXT: ret
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%a = load <8 x i64>, ptr %ap
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%val = trunc <8 x i64> %a to <8 x i32>
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store <8 x i32> %val, ptr %dest
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ret void
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}
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define void @store_trunc_v16i32i8(ptr %ap, ptr %dest) #0 {
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; Currently does not use the truncating store
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; VBITS_GE_256-LABEL: store_trunc_v16i32i8:
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; VBITS_GE_256: // %bb.0:
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; VBITS_GE_256-NEXT: ptrue p0.s, vl8
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; VBITS_GE_256-NEXT: mov x8, #8 // =0x8
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; VBITS_GE_256-NEXT: ld1w { z0.s }, p0/z, [x0, x8, lsl #2]
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; VBITS_GE_256-NEXT: ld1w { z1.s }, p0/z, [x0]
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; VBITS_GE_256-NEXT: mov w8, #8 // =0x8
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; VBITS_GE_256-NEXT: st1b { z0.s }, p0, [x1, x8]
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; VBITS_GE_256-NEXT: st1b { z1.s }, p0, [x1]
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; VBITS_GE_256-NEXT: ret
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;
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; VBITS_GE_512-LABEL: store_trunc_v16i32i8:
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; VBITS_GE_512: // %bb.0:
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; VBITS_GE_512-NEXT: ptrue p0.s, vl16
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; VBITS_GE_512-NEXT: ld1w { z0.s }, p0/z, [x0]
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; VBITS_GE_512-NEXT: st1b { z0.s }, p0, [x1]
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; VBITS_GE_512-NEXT: ret
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%a = load <16 x i32>, ptr %ap
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%val = trunc <16 x i32> %a to <16 x i8>
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store <16 x i8> %val, ptr %dest
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ret void
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}
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define void @store_trunc_v16i32i16(ptr %ap, ptr %dest) #0 {
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; VBITS_GE_256-LABEL: store_trunc_v16i32i16:
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; VBITS_GE_256: // %bb.0:
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; VBITS_GE_256-NEXT: ptrue p0.s, vl8
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; VBITS_GE_256-NEXT: mov x8, #8 // =0x8
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; VBITS_GE_256-NEXT: ld1w { z0.s }, p0/z, [x0, x8, lsl #2]
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; VBITS_GE_256-NEXT: ld1w { z1.s }, p0/z, [x0]
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; VBITS_GE_256-NEXT: st1h { z0.s }, p0, [x1, x8, lsl #1]
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; VBITS_GE_256-NEXT: st1h { z1.s }, p0, [x1]
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; VBITS_GE_256-NEXT: ret
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;
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; VBITS_GE_512-LABEL: store_trunc_v16i32i16:
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; VBITS_GE_512: // %bb.0:
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; VBITS_GE_512-NEXT: ptrue p0.s, vl16
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; VBITS_GE_512-NEXT: ld1w { z0.s }, p0/z, [x0]
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; VBITS_GE_512-NEXT: st1h { z0.s }, p0, [x1]
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; VBITS_GE_512-NEXT: ret
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%a = load <16 x i32>, ptr %ap
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%val = trunc <16 x i32> %a to <16 x i16>
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store <16 x i16> %val, ptr %dest
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ret void
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}
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define void @store_trunc_v32i16i8(ptr %ap, ptr %dest) #0 {
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; VBITS_GE_256-LABEL: store_trunc_v32i16i8:
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; VBITS_GE_256: // %bb.0:
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; VBITS_GE_256-NEXT: ptrue p0.h, vl16
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; VBITS_GE_256-NEXT: mov x8, #16 // =0x10
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; VBITS_GE_256-NEXT: ld1h { z0.h }, p0/z, [x0, x8, lsl #1]
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; VBITS_GE_256-NEXT: ld1h { z1.h }, p0/z, [x0]
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; VBITS_GE_256-NEXT: mov w8, #16 // =0x10
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; VBITS_GE_256-NEXT: st1b { z0.h }, p0, [x1, x8]
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; VBITS_GE_256-NEXT: st1b { z1.h }, p0, [x1]
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; VBITS_GE_256-NEXT: ret
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;
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; VBITS_GE_512-LABEL: store_trunc_v32i16i8:
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; VBITS_GE_512: // %bb.0:
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; VBITS_GE_512-NEXT: ptrue p0.h, vl32
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; VBITS_GE_512-NEXT: ld1h { z0.h }, p0/z, [x0]
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; VBITS_GE_512-NEXT: st1b { z0.h }, p0, [x1]
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; VBITS_GE_512-NEXT: ret
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%a = load <32 x i16>, ptr %ap
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%val = trunc <32 x i16> %a to <32 x i8>
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store <32 x i8> %val, ptr %dest
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ret void
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}
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define void @store_trunc_v4i64i32_min_vscale_one(ptr %src, ptr %dest) vscale_range(1,0) #0 {
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; CHECK-LABEL: store_trunc_v4i64i32_min_vscale_one:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldp q1, q0, [x0]
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; CHECK-NEXT: uzp1 v0.4s, v1.4s, v0.4s
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; CHECK-NEXT: str q0, [x1]
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; CHECK-NEXT: ret
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%ld = load <4 x i64>, ptr %src, align 4
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%trunc = trunc <4 x i64> %ld to <4 x i32>
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store <4 x i32> %trunc, ptr %dest, align 8
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ret void
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}
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define void @store_trunc_v4i64i32_min_vscale_two(ptr %src, ptr %dest) vscale_range(2,0) #0 {
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; CHECK-LABEL: store_trunc_v4i64i32_min_vscale_two:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.d, vl4
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; CHECK-NEXT: ld1d { z0.d }, p0/z, [x0]
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; CHECK-NEXT: st1w { z0.d }, p0, [x1]
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; CHECK-NEXT: ret
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%ld = load <4 x i64>, ptr %src, align 4
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%trunc = trunc <4 x i64> %ld to <4 x i32>
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store <4 x i32> %trunc, ptr %dest, align 8
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ret void
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}
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attributes #0 = { "target-features"="+sve" }
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