derek.holloway
7502bf64a4
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68 lines
2.1 KiB
LLVM
68 lines
2.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s
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; Check that vscale call is recognised by load/store reg/reg pattern and
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; partially folded, with the rest pulled out of the loop.
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define void @ld1w_reg_loop(ptr %addr) {
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; CHECK-LABEL: ld1w_reg_loop:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: ptrue p0.s
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; CHECK-NEXT: mov x8, xzr
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; CHECK-NEXT: cntw x9
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; CHECK-NEXT: .LBB0_1: // %vector.body
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; CHECK-NEXT: // =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: ld1w { z0.s }, p0/z, [x0, x8, lsl #2]
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; CHECK-NEXT: adds x8, x8, x9
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; CHECK-NEXT: b.ne .LBB0_1
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; CHECK-NEXT: // %bb.2: // %for.cond.cleanup
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; CHECK-NEXT: ret
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entry:
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%0 = call i64 @llvm.vscale.i64()
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%1 = shl i64 %0, 2
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br label %vector.body
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vector.body:
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%index = phi i64 [ 0, %entry ], [ %index.next, %vector.body ]
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%2 = getelementptr inbounds [32000 x i32], ptr %addr, i64 0, i64 %index
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%load = load volatile <vscale x 4 x i32>, ptr %2, align 16
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%index.next = add i64 %index, %1
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%3 = icmp eq i64 %index.next, 0
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br i1 %3, label %for.cond.cleanup, label %vector.body
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for.cond.cleanup:
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ret void
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}
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define void @st1w_reg_loop(ptr %addr, <vscale x 4 x i32> %val) {
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; CHECK-LABEL: st1w_reg_loop:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: ptrue p0.s
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; CHECK-NEXT: mov x8, xzr
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; CHECK-NEXT: cntw x9
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; CHECK-NEXT: .LBB1_1: // %vector.body
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; CHECK-NEXT: // =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: st1w { z0.s }, p0, [x0, x8, lsl #2]
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; CHECK-NEXT: adds x8, x8, x9
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; CHECK-NEXT: b.ne .LBB1_1
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; CHECK-NEXT: // %bb.2: // %for.cond.cleanup
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; CHECK-NEXT: ret
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entry:
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%0 = call i64 @llvm.vscale.i64()
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%1 = shl i64 %0, 2
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br label %vector.body
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vector.body:
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%index = phi i64 [ 0, %entry ], [ %index.next, %vector.body ]
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%2 = getelementptr inbounds [32000 x i32], ptr %addr, i64 0, i64 %index
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store volatile <vscale x 4 x i32> %val, ptr %2, align 16
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%index.next = add i64 %index, %1
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%3 = icmp eq i64 %index.next, 0
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br i1 %3, label %for.cond.cleanup, label %vector.body
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for.cond.cleanup:
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ret void
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}
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declare i64 @llvm.vscale.i64()
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