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TheRock/compiler/amd-llvm/llvm/test/CodeGen/AArch64/sve-int-imm.ll
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Flatten subprojects into a single base monorepo
2026-09-02 16:34:47 -07:00

555 lines
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve -use-constant-int-for-scalable-splat < %s | FileCheck %s
;
; SVE Arith Vector Immediate Unpredicated CodeGen
;
; ADD
define <vscale x 16 x i8> @add_i8_low(<vscale x 16 x i8> %a) {
; CHECK-LABEL: add_i8_low:
; CHECK: // %bb.0:
; CHECK-NEXT: add z0.b, z0.b, #30 // =0x1e
; CHECK-NEXT: ret
%res = add <vscale x 16 x i8> %a, splat(i8 30)
ret <vscale x 16 x i8> %res
}
define <vscale x 8 x i16> @add_i16_low(<vscale x 8 x i16> %a) {
; CHECK-LABEL: add_i16_low:
; CHECK: // %bb.0:
; CHECK-NEXT: add z0.h, z0.h, #30 // =0x1e
; CHECK-NEXT: ret
%res = add <vscale x 8 x i16> %a, splat(i16 30)
ret <vscale x 8 x i16> %res
}
define <vscale x 8 x i16> @add_i16_high(<vscale x 8 x i16> %a) {
; CHECK-LABEL: add_i16_high:
; CHECK: // %bb.0:
; CHECK-NEXT: add z0.h, z0.h, #1024 // =0x400
; CHECK-NEXT: ret
%res = add <vscale x 8 x i16> %a, splat(i16 1024)
ret <vscale x 8 x i16> %res
}
define <vscale x 4 x i32> @add_i32_low(<vscale x 4 x i32> %a) {
; CHECK-LABEL: add_i32_low:
; CHECK: // %bb.0:
; CHECK-NEXT: add z0.s, z0.s, #30 // =0x1e
; CHECK-NEXT: ret
%res = add <vscale x 4 x i32> %a, splat(i32 30)
ret <vscale x 4 x i32> %res
}
define <vscale x 4 x i32> @add_i32_high(<vscale x 4 x i32> %a) {
; CHECK-LABEL: add_i32_high:
; CHECK: // %bb.0:
; CHECK-NEXT: add z0.s, z0.s, #1024 // =0x400
; CHECK-NEXT: ret
%res = add <vscale x 4 x i32> %a, splat(i32 1024)
ret <vscale x 4 x i32> %res
}
define <vscale x 2 x i64> @add_i64_low(<vscale x 2 x i64> %a) {
; CHECK-LABEL: add_i64_low:
; CHECK: // %bb.0:
; CHECK-NEXT: add z0.d, z0.d, #30 // =0x1e
; CHECK-NEXT: ret
%res = add <vscale x 2 x i64> %a, splat(i64 30)
ret <vscale x 2 x i64> %res
}
define <vscale x 2 x i64> @add_i64_high(<vscale x 2 x i64> %a) {
; CHECK-LABEL: add_i64_high:
; CHECK: // %bb.0:
; CHECK-NEXT: add z0.d, z0.d, #1024 // =0x400
; CHECK-NEXT: ret
%res = add <vscale x 2 x i64> %a, splat(i64 1024)
ret <vscale x 2 x i64> %res
}
define <vscale x 16 x i8> @add_i8_signedness(<vscale x 16 x i8> %a) {
; CHECK-LABEL: add_i8_signedness:
; CHECK: // %bb.0:
; CHECK-NEXT: add z0.b, z0.b, #255 // =0xff
; CHECK-NEXT: ret
%res = add <vscale x 16 x i8> %a, splat(i8 255)
ret <vscale x 16 x i8> %res
}
define <vscale x 8 x i16> @add_i16_signedness(<vscale x 8 x i16> %a) {
; CHECK-LABEL: add_i16_signedness:
; CHECK: // %bb.0:
; CHECK-NEXT: add z0.h, z0.h, #65280 // =0xff00
; CHECK-NEXT: ret
%res = add <vscale x 8 x i16> %a, splat(i16 65280)
ret <vscale x 8 x i16> %res
}
; SUBR
define <vscale x 16 x i8> @subr_i8_low(<vscale x 16 x i8> %a) {
; CHECK-LABEL: subr_i8_low:
; CHECK: // %bb.0:
; CHECK-NEXT: subr z0.b, z0.b, #30 // =0x1e
; CHECK-NEXT: ret
%res = sub <vscale x 16 x i8> splat(i8 30), %a
ret <vscale x 16 x i8> %res
}
define <vscale x 8 x i16> @subr_i16_low(<vscale x 8 x i16> %a) {
; CHECK-LABEL: subr_i16_low:
; CHECK: // %bb.0:
; CHECK-NEXT: subr z0.h, z0.h, #30 // =0x1e
; CHECK-NEXT: ret
%res = sub <vscale x 8 x i16> splat(i16 30), %a
ret <vscale x 8 x i16> %res
}
define <vscale x 8 x i16> @subr_i16_high(<vscale x 8 x i16> %a) {
; CHECK-LABEL: subr_i16_high:
; CHECK: // %bb.0:
; CHECK-NEXT: subr z0.h, z0.h, #1024 // =0x400
; CHECK-NEXT: ret
%res = sub <vscale x 8 x i16> splat(i16 1024), %a
ret <vscale x 8 x i16> %res
}
define <vscale x 4 x i32> @subr_i32_low(<vscale x 4 x i32> %a) {
; CHECK-LABEL: subr_i32_low:
; CHECK: // %bb.0:
; CHECK-NEXT: subr z0.s, z0.s, #30 // =0x1e
; CHECK-NEXT: ret
%res = sub <vscale x 4 x i32> splat(i32 30), %a
ret <vscale x 4 x i32> %res
}
define <vscale x 4 x i32> @subr_i32_high(<vscale x 4 x i32> %a) {
; CHECK-LABEL: subr_i32_high:
; CHECK: // %bb.0:
; CHECK-NEXT: subr z0.s, z0.s, #1024 // =0x400
; CHECK-NEXT: ret
%res = sub <vscale x 4 x i32> splat(i32 1024), %a
ret <vscale x 4 x i32> %res
}
define <vscale x 2 x i64> @subr_i64_low(<vscale x 2 x i64> %a) {
; CHECK-LABEL: subr_i64_low:
; CHECK: // %bb.0:
; CHECK-NEXT: subr z0.d, z0.d, #30 // =0x1e
; CHECK-NEXT: ret
%res = sub <vscale x 2 x i64> splat(i64 30), %a
ret <vscale x 2 x i64> %res
}
define <vscale x 2 x i64> @subr_i64_high(<vscale x 2 x i64> %a) {
; CHECK-LABEL: subr_i64_high:
; CHECK: // %bb.0:
; CHECK-NEXT: subr z0.d, z0.d, #1024 // =0x400
; CHECK-NEXT: ret
%res = sub <vscale x 2 x i64> splat(i64 1024), %a
ret <vscale x 2 x i64> %res
}
; SUB
define <vscale x 16 x i8> @sub_i8_low(<vscale x 16 x i8> %a) {
; CHECK-LABEL: sub_i8_low:
; CHECK: // %bb.0:
; CHECK-NEXT: sub z0.b, z0.b, #30 // =0x1e
; CHECK-NEXT: ret
%res = sub <vscale x 16 x i8> %a, splat(i8 30)
ret <vscale x 16 x i8> %res
}
define <vscale x 8 x i16> @sub_i16_low(<vscale x 8 x i16> %a) {
; CHECK-LABEL: sub_i16_low:
; CHECK: // %bb.0:
; CHECK-NEXT: sub z0.h, z0.h, #30 // =0x1e
; CHECK-NEXT: ret
%res = sub <vscale x 8 x i16> %a, splat(i16 30)
ret <vscale x 8 x i16> %res
}
define <vscale x 8 x i16> @sub_i16_high(<vscale x 8 x i16> %a) {
; CHECK-LABEL: sub_i16_high:
; CHECK: // %bb.0:
; CHECK-NEXT: sub z0.h, z0.h, #1024 // =0x400
; CHECK-NEXT: ret
%res = sub <vscale x 8 x i16> %a, splat(i16 1024)
ret <vscale x 8 x i16> %res
}
define <vscale x 4 x i32> @sub_i32_low(<vscale x 4 x i32> %a) {
; CHECK-LABEL: sub_i32_low:
; CHECK: // %bb.0:
; CHECK-NEXT: sub z0.s, z0.s, #30 // =0x1e
; CHECK-NEXT: ret
%res = sub <vscale x 4 x i32> %a, splat(i32 30)
ret <vscale x 4 x i32> %res
}
define <vscale x 4 x i32> @sub_i32_high(<vscale x 4 x i32> %a) {
; CHECK-LABEL: sub_i32_high:
; CHECK: // %bb.0:
; CHECK-NEXT: sub z0.s, z0.s, #1024 // =0x400
; CHECK-NEXT: ret
%res = sub <vscale x 4 x i32> %a, splat(i32 1024)
ret <vscale x 4 x i32> %res
}
define <vscale x 2 x i64> @sub_i64_low(<vscale x 2 x i64> %a) {
; CHECK-LABEL: sub_i64_low:
; CHECK: // %bb.0:
; CHECK-NEXT: sub z0.d, z0.d, #30 // =0x1e
; CHECK-NEXT: ret
%res = sub <vscale x 2 x i64> %a, splat(i64 30)
ret <vscale x 2 x i64> %res
}
define <vscale x 2 x i64> @sub_i64_high(<vscale x 2 x i64> %a) {
; CHECK-LABEL: sub_i64_high:
; CHECK: // %bb.0:
; CHECK-NEXT: sub z0.d, z0.d, #1024 // =0x400
; CHECK-NEXT: ret
%res = sub <vscale x 2 x i64> %a, splat(i64 1024)
ret <vscale x 2 x i64> %res
}
; SUB via -ve add
define <vscale x 16 x i8> @addnve_i8_low(<vscale x 16 x i8> %a) {
; CHECK-LABEL: addnve_i8_low:
; CHECK: // %bb.0:
; CHECK-NEXT: add z0.b, z0.b, #226 // =0xe2
; CHECK-NEXT: ret
%res = add <vscale x 16 x i8> %a, splat(i8 -30)
ret <vscale x 16 x i8> %res
}
define <vscale x 8 x i16> @addnve_i16_low(<vscale x 8 x i16> %a) {
; CHECK-LABEL: addnve_i16_low:
; CHECK: // %bb.0:
; CHECK-NEXT: sub z0.h, z0.h, #30 // =0x1e
; CHECK-NEXT: ret
%res = add <vscale x 8 x i16> %a, splat(i16 -30)
ret <vscale x 8 x i16> %res
}
define <vscale x 8 x i16> @addnve_i16_high(<vscale x 8 x i16> %a) {
; CHECK-LABEL: addnve_i16_high:
; CHECK: // %bb.0:
; CHECK-NEXT: add z0.h, z0.h, #64512 // =0xfc00
; CHECK-NEXT: ret
%res = add <vscale x 8 x i16> %a, splat(i16 -1024)
ret <vscale x 8 x i16> %res
}
define <vscale x 4 x i32> @addnve_i32_low(<vscale x 4 x i32> %a) {
; CHECK-LABEL: addnve_i32_low:
; CHECK: // %bb.0:
; CHECK-NEXT: sub z0.s, z0.s, #30 // =0x1e
; CHECK-NEXT: ret
%res = add <vscale x 4 x i32> %a, splat(i32 -30)
ret <vscale x 4 x i32> %res
}
define <vscale x 4 x i32> @addnve_i32_high(<vscale x 4 x i32> %a) {
; CHECK-LABEL: addnve_i32_high:
; CHECK: // %bb.0:
; CHECK-NEXT: sub z0.s, z0.s, #1024 // =0x400
; CHECK-NEXT: ret
%res = add <vscale x 4 x i32> %a, splat(i32 -1024)
ret <vscale x 4 x i32> %res
}
define <vscale x 2 x i64> @addnve_i64_low(<vscale x 2 x i64> %a) {
; CHECK-LABEL: addnve_i64_low:
; CHECK: // %bb.0:
; CHECK-NEXT: sub z0.d, z0.d, #30 // =0x1e
; CHECK-NEXT: ret
%res = add <vscale x 2 x i64> %a, splat(i64 -30)
ret <vscale x 2 x i64> %res
}
define <vscale x 2 x i64> @addnve_i64_high(<vscale x 2 x i64> %a) {
; CHECK-LABEL: addnve_i64_high:
; CHECK: // %bb.0:
; CHECK-NEXT: sub z0.d, z0.d, #1024 // =0x400
; CHECK-NEXT: ret
%res = add <vscale x 2 x i64> %a, splat(i64 -1024)
ret <vscale x 2 x i64> %res
}
; SQADD
define <vscale x 16 x i8> @sqadd_i8_low(<vscale x 16 x i8> %a) {
; CHECK-LABEL: sqadd_i8_low:
; CHECK: // %bb.0:
; CHECK-NEXT: sqadd z0.b, z0.b, #30 // =0x1e
; CHECK-NEXT: ret
%res = call <vscale x 16 x i8> @llvm.sadd.sat.nxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> splat(i8 30))
ret <vscale x 16 x i8> %res
}
define <vscale x 8 x i16> @sqadd_i16_low(<vscale x 8 x i16> %a) {
; CHECK-LABEL: sqadd_i16_low:
; CHECK: // %bb.0:
; CHECK-NEXT: sqadd z0.h, z0.h, #30 // =0x1e
; CHECK-NEXT: ret
%res = call <vscale x 8 x i16> @llvm.sadd.sat.nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> splat(i16 30))
ret <vscale x 8 x i16> %res
}
define <vscale x 8 x i16> @sqadd_i16_high(<vscale x 8 x i16> %a) {
; CHECK-LABEL: sqadd_i16_high:
; CHECK: // %bb.0:
; CHECK-NEXT: sqadd z0.h, z0.h, #1024 // =0x400
; CHECK-NEXT: ret
%res = call <vscale x 8 x i16> @llvm.sadd.sat.nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> splat(i16 1024))
ret <vscale x 8 x i16> %res
}
define <vscale x 4 x i32> @sqadd_i32_low(<vscale x 4 x i32> %a) {
; CHECK-LABEL: sqadd_i32_low:
; CHECK: // %bb.0:
; CHECK-NEXT: sqadd z0.s, z0.s, #30 // =0x1e
; CHECK-NEXT: ret
%res = call <vscale x 4 x i32> @llvm.sadd.sat.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> splat(i32 30))
ret <vscale x 4 x i32> %res
}
define <vscale x 4 x i32> @sqadd_i32_high(<vscale x 4 x i32> %a) {
; CHECK-LABEL: sqadd_i32_high:
; CHECK: // %bb.0:
; CHECK-NEXT: sqadd z0.s, z0.s, #1024 // =0x400
; CHECK-NEXT: ret
%res = call <vscale x 4 x i32> @llvm.sadd.sat.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> splat(i32 1024))
ret <vscale x 4 x i32> %res
}
define <vscale x 2 x i64> @sqadd_i64_low(<vscale x 2 x i64> %a) {
; CHECK-LABEL: sqadd_i64_low:
; CHECK: // %bb.0:
; CHECK-NEXT: sqadd z0.d, z0.d, #30 // =0x1e
; CHECK-NEXT: ret
%res = call <vscale x 2 x i64> @llvm.sadd.sat.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> splat(i64 30))
ret <vscale x 2 x i64> %res
}
define <vscale x 2 x i64> @sqadd_i64_high(<vscale x 2 x i64> %a) {
; CHECK-LABEL: sqadd_i64_high:
; CHECK: // %bb.0:
; CHECK-NEXT: sqadd z0.d, z0.d, #1024 // =0x400
; CHECK-NEXT: ret
%res = call <vscale x 2 x i64> @llvm.sadd.sat.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> splat(i64 1024))
ret <vscale x 2 x i64> %res
}
; UQADD
define <vscale x 16 x i8> @uqadd_i8_low(<vscale x 16 x i8> %a) {
; CHECK-LABEL: uqadd_i8_low:
; CHECK: // %bb.0:
; CHECK-NEXT: uqadd z0.b, z0.b, #30 // =0x1e
; CHECK-NEXT: ret
%res = call <vscale x 16 x i8> @llvm.uadd.sat.nxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> splat(i8 30))
ret <vscale x 16 x i8> %res
}
define <vscale x 8 x i16> @uqadd_i16_low(<vscale x 8 x i16> %a) {
; CHECK-LABEL: uqadd_i16_low:
; CHECK: // %bb.0:
; CHECK-NEXT: uqadd z0.h, z0.h, #30 // =0x1e
; CHECK-NEXT: ret
%res = call <vscale x 8 x i16> @llvm.uadd.sat.nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> splat(i16 30))
ret <vscale x 8 x i16> %res
}
define <vscale x 8 x i16> @uqadd_i16_high(<vscale x 8 x i16> %a) {
; CHECK-LABEL: uqadd_i16_high:
; CHECK: // %bb.0:
; CHECK-NEXT: uqadd z0.h, z0.h, #1024 // =0x400
; CHECK-NEXT: ret
%res = call <vscale x 8 x i16> @llvm.uadd.sat.nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> splat(i16 1024))
ret <vscale x 8 x i16> %res
}
define <vscale x 4 x i32> @uqadd_i32_low(<vscale x 4 x i32> %a) {
; CHECK-LABEL: uqadd_i32_low:
; CHECK: // %bb.0:
; CHECK-NEXT: uqadd z0.s, z0.s, #30 // =0x1e
; CHECK-NEXT: ret
%res = call <vscale x 4 x i32> @llvm.uadd.sat.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> splat(i32 30))
ret <vscale x 4 x i32> %res
}
define <vscale x 4 x i32> @uqadd_i32_high(<vscale x 4 x i32> %a) {
; CHECK-LABEL: uqadd_i32_high:
; CHECK: // %bb.0:
; CHECK-NEXT: uqadd z0.s, z0.s, #1024 // =0x400
; CHECK-NEXT: ret
%res = call <vscale x 4 x i32> @llvm.uadd.sat.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> splat(i32 1024))
ret <vscale x 4 x i32> %res
}
define <vscale x 2 x i64> @uqadd_i64_low(<vscale x 2 x i64> %a) {
; CHECK-LABEL: uqadd_i64_low:
; CHECK: // %bb.0:
; CHECK-NEXT: uqadd z0.d, z0.d, #30 // =0x1e
; CHECK-NEXT: ret
%res = call <vscale x 2 x i64> @llvm.uadd.sat.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> splat(i64 30))
ret <vscale x 2 x i64> %res
}
define <vscale x 2 x i64> @uqadd_i64_high(<vscale x 2 x i64> %a) {
; CHECK-LABEL: uqadd_i64_high:
; CHECK: // %bb.0:
; CHECK-NEXT: uqadd z0.d, z0.d, #1024 // =0x400
; CHECK-NEXT: ret
%res = call <vscale x 2 x i64> @llvm.uadd.sat.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> splat(i64 1024))
ret <vscale x 2 x i64> %res
}
; SQSUB
define <vscale x 16 x i8> @sqsub_i8_low(<vscale x 16 x i8> %a) {
; CHECK-LABEL: sqsub_i8_low:
; CHECK: // %bb.0:
; CHECK-NEXT: sqsub z0.b, z0.b, #30 // =0x1e
; CHECK-NEXT: ret
%res = call <vscale x 16 x i8> @llvm.ssub.sat.nxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> splat(i8 30))
ret <vscale x 16 x i8> %res
}
define <vscale x 8 x i16> @sqsub_i16_low(<vscale x 8 x i16> %a) {
; CHECK-LABEL: sqsub_i16_low:
; CHECK: // %bb.0:
; CHECK-NEXT: sqsub z0.h, z0.h, #30 // =0x1e
; CHECK-NEXT: ret
%res = call <vscale x 8 x i16> @llvm.ssub.sat.nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> splat(i16 30))
ret <vscale x 8 x i16> %res
}
define <vscale x 8 x i16> @sqsub_i16_high(<vscale x 8 x i16> %a) {
; CHECK-LABEL: sqsub_i16_high:
; CHECK: // %bb.0:
; CHECK-NEXT: sqsub z0.h, z0.h, #1024 // =0x400
; CHECK-NEXT: ret
%res = call <vscale x 8 x i16> @llvm.ssub.sat.nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> splat(i16 1024))
ret <vscale x 8 x i16> %res
}
define <vscale x 4 x i32> @sqsub_i32_low(<vscale x 4 x i32> %a) {
; CHECK-LABEL: sqsub_i32_low:
; CHECK: // %bb.0:
; CHECK-NEXT: sqsub z0.s, z0.s, #30 // =0x1e
; CHECK-NEXT: ret
%res = call <vscale x 4 x i32> @llvm.ssub.sat.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> splat(i32 30))
ret <vscale x 4 x i32> %res
}
define <vscale x 4 x i32> @sqsub_i32_high(<vscale x 4 x i32> %a) {
; CHECK-LABEL: sqsub_i32_high:
; CHECK: // %bb.0:
; CHECK-NEXT: sqsub z0.s, z0.s, #1024 // =0x400
; CHECK-NEXT: ret
%res = call <vscale x 4 x i32> @llvm.ssub.sat.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> splat(i32 1024))
ret <vscale x 4 x i32> %res
}
define <vscale x 2 x i64> @sqsub_i64_low(<vscale x 2 x i64> %a) {
; CHECK-LABEL: sqsub_i64_low:
; CHECK: // %bb.0:
; CHECK-NEXT: sqsub z0.d, z0.d, #30 // =0x1e
; CHECK-NEXT: ret
%res = call <vscale x 2 x i64> @llvm.ssub.sat.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> splat(i64 30))
ret <vscale x 2 x i64> %res
}
define <vscale x 2 x i64> @sqsub_i64_high(<vscale x 2 x i64> %a) {
; CHECK-LABEL: sqsub_i64_high:
; CHECK: // %bb.0:
; CHECK-NEXT: sqsub z0.d, z0.d, #1024 // =0x400
; CHECK-NEXT: ret
%res = call <vscale x 2 x i64> @llvm.ssub.sat.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> splat(i64 1024))
ret <vscale x 2 x i64> %res
}
; UQSUB
define <vscale x 16 x i8> @uqsub_i8_low(<vscale x 16 x i8> %a) {
; CHECK-LABEL: uqsub_i8_low:
; CHECK: // %bb.0:
; CHECK-NEXT: uqsub z0.b, z0.b, #30 // =0x1e
; CHECK-NEXT: ret
%res = call <vscale x 16 x i8> @llvm.usub.sat.nxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> splat(i8 30))
ret <vscale x 16 x i8> %res
}
define <vscale x 8 x i16> @uqsub_i16_low(<vscale x 8 x i16> %a) {
; CHECK-LABEL: uqsub_i16_low:
; CHECK: // %bb.0:
; CHECK-NEXT: uqsub z0.h, z0.h, #30 // =0x1e
; CHECK-NEXT: ret
%res = call <vscale x 8 x i16> @llvm.usub.sat.nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> splat(i16 30))
ret <vscale x 8 x i16> %res
}
define <vscale x 8 x i16> @uqsub_i16_high(<vscale x 8 x i16> %a) {
; CHECK-LABEL: uqsub_i16_high:
; CHECK: // %bb.0:
; CHECK-NEXT: uqsub z0.h, z0.h, #1024 // =0x400
; CHECK-NEXT: ret
%res = call <vscale x 8 x i16> @llvm.usub.sat.nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> splat(i16 1024))
ret <vscale x 8 x i16> %res
}
define <vscale x 4 x i32> @uqsub_i32_low(<vscale x 4 x i32> %a) {
; CHECK-LABEL: uqsub_i32_low:
; CHECK: // %bb.0:
; CHECK-NEXT: uqsub z0.s, z0.s, #30 // =0x1e
; CHECK-NEXT: ret
%res = call <vscale x 4 x i32> @llvm.usub.sat.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> splat(i32 30))
ret <vscale x 4 x i32> %res
}
define <vscale x 4 x i32> @uqsub_i32_high(<vscale x 4 x i32> %a) {
; CHECK-LABEL: uqsub_i32_high:
; CHECK: // %bb.0:
; CHECK-NEXT: uqsub z0.s, z0.s, #1024 // =0x400
; CHECK-NEXT: ret
%res = call <vscale x 4 x i32> @llvm.usub.sat.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> splat(i32 1024))
ret <vscale x 4 x i32> %res
}
define <vscale x 2 x i64> @uqsub_i64_low(<vscale x 2 x i64> %a) {
; CHECK-LABEL: uqsub_i64_low:
; CHECK: // %bb.0:
; CHECK-NEXT: uqsub z0.d, z0.d, #30 // =0x1e
; CHECK-NEXT: ret
%res = call <vscale x 2 x i64> @llvm.usub.sat.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> splat(i64 30))
ret <vscale x 2 x i64> %res
}
define <vscale x 2 x i64> @uqsub_i64_high(<vscale x 2 x i64> %a) {
; CHECK-LABEL: uqsub_i64_high:
; CHECK: // %bb.0:
; CHECK-NEXT: uqsub z0.d, z0.d, #1024 // =0x400
; CHECK-NEXT: ret
%res = call <vscale x 2 x i64> @llvm.usub.sat.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> splat(i64 1024))
ret <vscale x 2 x i64> %res
}
declare <vscale x 16 x i8> @llvm.sadd.sat.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>)
declare <vscale x 8 x i16> @llvm.sadd.sat.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>)
declare <vscale x 4 x i32> @llvm.sadd.sat.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>)
declare <vscale x 2 x i64> @llvm.sadd.sat.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>)
declare <vscale x 16 x i8> @llvm.uadd.sat.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>)
declare <vscale x 8 x i16> @llvm.uadd.sat.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>)
declare <vscale x 4 x i32> @llvm.uadd.sat.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>)
declare <vscale x 2 x i64> @llvm.uadd.sat.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>)
declare <vscale x 16 x i8> @llvm.ssub.sat.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>)
declare <vscale x 8 x i16> @llvm.ssub.sat.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>)
declare <vscale x 4 x i32> @llvm.ssub.sat.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>)
declare <vscale x 2 x i64> @llvm.ssub.sat.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>)
declare <vscale x 16 x i8> @llvm.usub.sat.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>)
declare <vscale x 8 x i16> @llvm.usub.sat.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>)
declare <vscale x 4 x i32> @llvm.usub.sat.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>)
declare <vscale x 2 x i64> @llvm.usub.sat.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>)
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