derek.holloway
7502bf64a4
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312 lines
9.8 KiB
LLVM
312 lines
9.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -enable-subreg-liveness -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s
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; RUN: llc -enable-subreg-liveness -mtriple=aarch64-linux-gnu -mattr=+sme -force-streaming < %s | FileCheck %s
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;
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; Testing prfop encodings
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;
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define void @test_svprf_pldl1strm(<vscale x 16 x i1> %pg, ptr %base) {
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; CHECK-LABEL: test_svprf_pldl1strm:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: prfb pldl1strm, p0, [x0]
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; CHECK-NEXT: ret
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entry:
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tail call void @llvm.aarch64.sve.prf.nxv16i1(<vscale x 16 x i1> %pg, ptr %base, i32 1)
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ret void
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}
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define void @test_svprf_pldl2keep(<vscale x 16 x i1> %pg, ptr %base) {
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; CHECK-LABEL: test_svprf_pldl2keep:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: prfb pldl2keep, p0, [x0]
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; CHECK-NEXT: ret
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entry:
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tail call void @llvm.aarch64.sve.prf.nxv16i1(<vscale x 16 x i1> %pg, ptr %base, i32 2)
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ret void
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}
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define void @test_svprf_pldl2strm(<vscale x 16 x i1> %pg, ptr %base) {
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; CHECK-LABEL: test_svprf_pldl2strm:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: prfb pldl2strm, p0, [x0]
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; CHECK-NEXT: ret
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entry:
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tail call void @llvm.aarch64.sve.prf.nxv16i1(<vscale x 16 x i1> %pg, ptr %base, i32 3)
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ret void
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}
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define void @test_svprf_pldl3keep(<vscale x 16 x i1> %pg, ptr %base) {
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; CHECK-LABEL: test_svprf_pldl3keep:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: prfb pldl3keep, p0, [x0]
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; CHECK-NEXT: ret
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entry:
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tail call void @llvm.aarch64.sve.prf.nxv16i1(<vscale x 16 x i1> %pg, ptr %base, i32 4)
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ret void
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}
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define void @test_svprf_pldl3strm(<vscale x 16 x i1> %pg, ptr %base) {
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; CHECK-LABEL: test_svprf_pldl3strm:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: prfb pldl3strm, p0, [x0]
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; CHECK-NEXT: ret
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entry:
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tail call void @llvm.aarch64.sve.prf.nxv16i1(<vscale x 16 x i1> %pg, ptr %base, i32 5)
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ret void
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}
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define void @test_svprf_pstl1keep(<vscale x 16 x i1> %pg, ptr %base) {
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; CHECK-LABEL: test_svprf_pstl1keep:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: prfb pstl1keep, p0, [x0]
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; CHECK-NEXT: ret
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entry:
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tail call void @llvm.aarch64.sve.prf.nxv16i1(<vscale x 16 x i1> %pg, ptr %base, i32 8)
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ret void
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}
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define void @test_svprf_pstl1strm(<vscale x 16 x i1> %pg, ptr %base) {
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; CHECK-LABEL: test_svprf_pstl1strm:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: prfb pstl1strm, p0, [x0]
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; CHECK-NEXT: ret
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entry:
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tail call void @llvm.aarch64.sve.prf.nxv16i1(<vscale x 16 x i1> %pg, ptr %base, i32 9)
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ret void
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}
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define void @test_svprf_pstl2keep(<vscale x 16 x i1> %pg, ptr %base) {
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; CHECK-LABEL: test_svprf_pstl2keep:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: prfb pstl2keep, p0, [x0]
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; CHECK-NEXT: ret
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entry:
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tail call void @llvm.aarch64.sve.prf.nxv16i1(<vscale x 16 x i1> %pg, ptr %base, i32 10)
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ret void
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}
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define void @test_svprf_pstl2strm(<vscale x 16 x i1> %pg, ptr %base) {
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; CHECK-LABEL: test_svprf_pstl2strm:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: prfb pstl2strm, p0, [x0]
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; CHECK-NEXT: ret
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entry:
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tail call void @llvm.aarch64.sve.prf.nxv16i1(<vscale x 16 x i1> %pg, ptr %base, i32 11)
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ret void
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}
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define void @test_svprf_pstl3keep(<vscale x 16 x i1> %pg, ptr %base) {
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; CHECK-LABEL: test_svprf_pstl3keep:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: prfb pstl3keep, p0, [x0]
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; CHECK-NEXT: ret
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entry:
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tail call void @llvm.aarch64.sve.prf.nxv16i1(<vscale x 16 x i1> %pg, ptr %base, i32 12)
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ret void
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}
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define void @test_svprf_pstl3strm(<vscale x 16 x i1> %pg, ptr %base) {
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; CHECK-LABEL: test_svprf_pstl3strm:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: prfb pstl3strm, p0, [x0]
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; CHECK-NEXT: ret
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entry:
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tail call void @llvm.aarch64.sve.prf.nxv16i1(<vscale x 16 x i1> %pg, ptr %base, i32 13)
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ret void
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}
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;
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; Testing imm limits of SI form
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;
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define void @test_svprf_vnum_under(<vscale x 16 x i1> %pg, ptr %base) {
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; CHECK-LABEL: test_svprf_vnum_under:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: rdvl x8, #1
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; CHECK-NEXT: mov x9, #-528 // =0xfffffffffffffdf0
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; CHECK-NEXT: lsr x8, x8, #4
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; CHECK-NEXT: mul x8, x8, x9
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; CHECK-NEXT: prfb pstl3strm, p0, [x0, x8]
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; CHECK-NEXT: ret
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entry:
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%gep = getelementptr inbounds <vscale x 16 x i8>, ptr %base, i64 -33, i64 0
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tail call void @llvm.aarch64.sve.prf.nxv16i1(<vscale x 16 x i1> %pg, ptr %gep, i32 13)
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ret void
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}
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define void @test_svprf_vnum_min(<vscale x 16 x i1> %pg, ptr %base) {
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; CHECK-LABEL: test_svprf_vnum_min:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: prfb pstl3strm, p0, [x0, #-32, mul vl]
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; CHECK-NEXT: ret
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entry:
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%gep = getelementptr inbounds <vscale x 16 x i8>, ptr %base, i64 -32, i64 0
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tail call void @llvm.aarch64.sve.prf.nxv16i1(<vscale x 16 x i1> %pg, ptr %gep, i32 13)
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ret void
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}
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define void @test_svprf_vnum_over(<vscale x 16 x i1> %pg, ptr %base) {
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; CHECK-LABEL: test_svprf_vnum_over:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: rdvl x8, #1
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; CHECK-NEXT: mov w9, #512 // =0x200
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; CHECK-NEXT: lsr x8, x8, #4
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; CHECK-NEXT: mul x8, x8, x9
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; CHECK-NEXT: prfb pstl3strm, p0, [x0, x8]
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; CHECK-NEXT: ret
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entry:
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%gep = getelementptr inbounds <vscale x 16 x i8>, ptr %base, i64 32, i64 0
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tail call void @llvm.aarch64.sve.prf.nxv16i1(<vscale x 16 x i1> %pg, ptr %gep, i32 13)
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ret void
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}
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define void @test_svprf_vnum_max(<vscale x 16 x i1> %pg, ptr %base) {
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; CHECK-LABEL: test_svprf_vnum_max:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: prfb pstl3strm, p0, [x0, #31, mul vl]
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; CHECK-NEXT: ret
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entry:
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%gep = getelementptr inbounds <vscale x 16 x i8>, ptr %base, i64 31, i64 0
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tail call void @llvm.aarch64.sve.prf.nxv16i1(<vscale x 16 x i1> %pg, ptr %gep, i32 13)
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ret void
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}
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;
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; scalar contiguous
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;
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define void @test_svprfb(<vscale x 16 x i1> %pg, ptr %base) {
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; CHECK-LABEL: test_svprfb:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: prfb pldl1keep, p0, [x0]
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; CHECK-NEXT: ret
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entry:
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tail call void @llvm.aarch64.sve.prf.nxv16i1(<vscale x 16 x i1> %pg, ptr %base, i32 0)
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ret void
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}
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define void @test_svprfh(<vscale x 8 x i1> %pg, ptr %base) {
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; CHECK-LABEL: test_svprfh:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: prfh pldl1keep, p0, [x0]
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; CHECK-NEXT: ret
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entry:
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tail call void @llvm.aarch64.sve.prf.nxv8i1(<vscale x 8 x i1> %pg, ptr %base, i32 0)
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ret void
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}
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define void @test_svprfw(<vscale x 4 x i1> %pg, ptr %base) {
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; CHECK-LABEL: test_svprfw:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: prfw pldl1keep, p0, [x0]
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; CHECK-NEXT: ret
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entry:
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tail call void @llvm.aarch64.sve.prf.nxv4i1(<vscale x 4 x i1> %pg, ptr %base, i32 0)
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ret void
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}
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define void @test_svprfd(<vscale x 2 x i1> %pg, ptr %base) {
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; CHECK-LABEL: test_svprfd:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: prfd pldl1keep, p0, [x0]
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; CHECK-NEXT: ret
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entry:
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tail call void @llvm.aarch64.sve.prf.nxv2i1(<vscale x 2 x i1> %pg, ptr %base, i32 0)
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ret void
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}
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;
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; scalar + imm contiguous
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;
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; imm form of prfb is tested above
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define void @test_svprfh_vnum(<vscale x 8 x i1> %pg, ptr %base) {
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; CHECK-LABEL: test_svprfh_vnum:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: prfh pstl3strm, p0, [x0, #31, mul vl]
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; CHECK-NEXT: ret
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entry:
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%gep = getelementptr <vscale x 8 x i16>, ptr %base, i64 31
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%addr = bitcast ptr %gep to ptr
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tail call void @llvm.aarch64.sve.prf.nxv8i1(<vscale x 8 x i1> %pg, ptr %addr, i32 13)
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ret void
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}
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define void @test_svprfw_vnum(<vscale x 4 x i1> %pg, ptr %base) {
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; CHECK-LABEL: test_svprfw_vnum:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: prfw pstl3strm, p0, [x0, #31, mul vl]
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; CHECK-NEXT: ret
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entry:
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%gep = getelementptr <vscale x 4 x i32>, ptr %base, i64 31
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%addr = bitcast ptr %gep to ptr
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tail call void @llvm.aarch64.sve.prf.nxv4i1(<vscale x 4 x i1> %pg, ptr %addr, i32 13)
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ret void
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}
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define void @test_svprfd_vnum(<vscale x 2 x i1> %pg, ptr %base) {
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; CHECK-LABEL: test_svprfd_vnum:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: prfd pstl3strm, p0, [x0, #31, mul vl]
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; CHECK-NEXT: ret
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entry:
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%gep = getelementptr <vscale x 2 x i64>, ptr %base, i64 31
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%addr = bitcast ptr %gep to ptr
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tail call void @llvm.aarch64.sve.prf.nxv2i1(<vscale x 2 x i1> %pg, ptr %addr, i32 13)
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ret void
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}
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;
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; scalar + scaled scalar contiguous
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;
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define void @test_svprfb_ss(<vscale x 16 x i1> %pg, ptr %base, i64 %offset) {
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; CHECK-LABEL: test_svprfb_ss:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: prfb pstl3strm, p0, [x0, x1]
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; CHECK-NEXT: ret
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entry:
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%addr = getelementptr i8, ptr %base, i64 %offset
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tail call void @llvm.aarch64.sve.prf.nxv16i1(<vscale x 16 x i1> %pg, ptr %addr, i32 13)
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ret void
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}
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define void @test_svprfh_ss(<vscale x 8 x i1> %pg, ptr %base, i64 %offset) {
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; CHECK-LABEL: test_svprfh_ss:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: prfh pstl3strm, p0, [x0, x1, lsl #1]
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; CHECK-NEXT: ret
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entry:
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%gep = getelementptr i16, ptr %base, i64 %offset
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tail call void @llvm.aarch64.sve.prf.nxv8i1(<vscale x 8 x i1> %pg, ptr %gep, i32 13)
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ret void
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}
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define void @test_svprfw_ss(<vscale x 4 x i1> %pg, ptr %base, i64 %offset) {
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; CHECK-LABEL: test_svprfw_ss:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: prfw pstl3strm, p0, [x0, x1, lsl #2]
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; CHECK-NEXT: ret
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entry:
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%gep = getelementptr i32, ptr %base, i64 %offset
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tail call void @llvm.aarch64.sve.prf.nxv4i1(<vscale x 4 x i1> %pg, ptr %gep, i32 13)
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ret void
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}
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define void @test_svprfd_ss(<vscale x 2 x i1> %pg, ptr %base, i64 %offset) {
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; CHECK-LABEL: test_svprfd_ss:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: prfd pstl3strm, p0, [x0, x1, lsl #3]
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; CHECK-NEXT: ret
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entry:
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%gep = getelementptr i64, ptr %base, i64 %offset
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tail call void @llvm.aarch64.sve.prf.nxv2i1(<vscale x 2 x i1> %pg, ptr %gep, i32 13)
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ret void
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}
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declare void @llvm.aarch64.sve.prf.nxv16i1(<vscale x 16 x i1>, ptr, i32)
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declare void @llvm.aarch64.sve.prf.nxv8i1(<vscale x 8 x i1>, ptr, i32)
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declare void @llvm.aarch64.sve.prf.nxv4i1(<vscale x 4 x i1>, ptr, i32)
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declare void @llvm.aarch64.sve.prf.nxv2i1(<vscale x 2 x i1>, ptr, i32)
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