derek.holloway
7502bf64a4
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225 lines
13 KiB
LLVM
225 lines
13 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=aarch64--linux-gnu -mattr=+sve < %s | FileCheck %s
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; PRFB <prfop>, <Pg>, [<Xn|SP>, <Zm>.S, <mod>] -> 32-bit indexes
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define void @llvm_aarch64_sve_prfb_gather_uxtw_index_nx4vi32(<vscale x 4 x i1> %Pg, ptr %base, <vscale x 4 x i32> %indexes) nounwind {
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; CHECK-LABEL: llvm_aarch64_sve_prfb_gather_uxtw_index_nx4vi32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: prfb pldl1strm, p0, [x0, z0.s, uxtw]
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; CHECK-NEXT: ret
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call void @llvm.aarch64.sve.prfb.gather.uxtw.index.nx4vi32(<vscale x 4 x i1> %Pg, ptr %base, <vscale x 4 x i32> %indexes, i32 1)
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ret void
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}
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define void @llvm_aarch64_sve_prfb_gather_scaled_sxtw_index_nx4vi32(<vscale x 4 x i1> %Pg, ptr %base, <vscale x 4 x i32> %indexes) nounwind {
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; CHECK-LABEL: llvm_aarch64_sve_prfb_gather_scaled_sxtw_index_nx4vi32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: prfb pldl1strm, p0, [x0, z0.s, sxtw]
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; CHECK-NEXT: ret
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call void @llvm.aarch64.sve.prfb.gather.sxtw.index.nx4vi32(<vscale x 4 x i1> %Pg, ptr %base, <vscale x 4 x i32> %indexes, i32 1)
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ret void
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}
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; PRFB <prfop>, <Pg>, [<Xn|SP>, <Zm>.D, <mod>] -> 32-bit unpacked indexes
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define void @llvm_aarch64_sve_prfb_gather_uxtw_index_nx2vi64(<vscale x 2 x i1> %Pg, ptr %base, <vscale x 2 x i32> %indexes) nounwind {
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; CHECK-LABEL: llvm_aarch64_sve_prfb_gather_uxtw_index_nx2vi64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: prfb pldl1strm, p0, [x0, z0.d, uxtw]
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; CHECK-NEXT: ret
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call void @llvm.aarch64.sve.prfb.gather.uxtw.index.nx2vi64(<vscale x 2 x i1> %Pg, ptr %base, <vscale x 2 x i32> %indexes, i32 1)
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ret void
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}
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define void @llvm_aarch64_sve_prfb_gather_scaled_sxtw_index_nx2vi64(<vscale x 2 x i1> %Pg, ptr %base, <vscale x 2 x i32> %indexes) nounwind {
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; CHECK-LABEL: llvm_aarch64_sve_prfb_gather_scaled_sxtw_index_nx2vi64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: prfb pldl1strm, p0, [x0, z0.d, sxtw]
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; CHECK-NEXT: ret
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call void @llvm.aarch64.sve.prfb.gather.sxtw.index.nx2vi64(<vscale x 2 x i1> %Pg, ptr %base, <vscale x 2 x i32> %indexes, i32 1)
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ret void
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}
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; PRFB <prfop>, <Pg>, [<Xn|SP>, <Zm>.D] -> 64-bit indexes
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define void @llvm_aarch64_sve_prfb_gather_scaled_nx2vi64(<vscale x 2 x i1> %Pg, ptr %base, <vscale x 2 x i64> %indexes) nounwind {
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; CHECK-LABEL: llvm_aarch64_sve_prfb_gather_scaled_nx2vi64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: prfb pldl1strm, p0, [x0, z0.d]
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; CHECK-NEXT: ret
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call void @llvm.aarch64.sve.prfb.gather.index.nx2vi64(<vscale x 2 x i1> %Pg, ptr %base, <vscale x 2 x i64> %indexes, i32 1)
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ret void
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}
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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; PRFH <prfop>, <Pg>, [<Xn|SP>, <Zm>.S, <mod>] -> 32-bit indexes
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define void @llvm_aarch64_sve_prfh_gather_uxtw_index_nx4vi32(<vscale x 4 x i1> %Pg, ptr %base, <vscale x 4 x i32> %indexes) nounwind {
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; CHECK-LABEL: llvm_aarch64_sve_prfh_gather_uxtw_index_nx4vi32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: prfh pldl1strm, p0, [x0, z0.s, uxtw #1]
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; CHECK-NEXT: ret
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call void @llvm.aarch64.sve.prfh.gather.uxtw.index.nx4vi32(<vscale x 4 x i1> %Pg, ptr %base, <vscale x 4 x i32> %indexes, i32 1)
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ret void
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}
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define void @llvm_aarch64_sve_prfh_gather_scaled_sxtw_index_nx4vi32(<vscale x 4 x i1> %Pg, ptr %base, <vscale x 4 x i32> %indexes) nounwind {
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; CHECK-LABEL: llvm_aarch64_sve_prfh_gather_scaled_sxtw_index_nx4vi32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: prfh pldl1strm, p0, [x0, z0.s, sxtw #1]
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; CHECK-NEXT: ret
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call void @llvm.aarch64.sve.prfh.gather.sxtw.index.nx4vi32(<vscale x 4 x i1> %Pg, ptr %base, <vscale x 4 x i32> %indexes, i32 1)
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ret void
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}
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; PRFH <prfop>, <Pg>, [<Xn|SP>, <Zm>.D, <mod> #1] -> 32-bit unpacked indexes
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define void @llvm_aarch64_sve_prfh_gather_uxtw_index_nx2vi64(<vscale x 2 x i1> %Pg, ptr %base, <vscale x 2 x i32> %indexes) nounwind {
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; CHECK-LABEL: llvm_aarch64_sve_prfh_gather_uxtw_index_nx2vi64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: prfh pldl1strm, p0, [x0, z0.d, uxtw #1]
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; CHECK-NEXT: ret
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call void @llvm.aarch64.sve.prfh.gather.uxtw.index.nx2vi64(<vscale x 2 x i1> %Pg, ptr %base, <vscale x 2 x i32> %indexes, i32 1)
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ret void
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}
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define void @llvm_aarch64_sve_prfh_gather_scaled_sxtw_index_nx2vi64(<vscale x 2 x i1> %Pg, ptr %base, <vscale x 2 x i32> %indexes) nounwind {
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; CHECK-LABEL: llvm_aarch64_sve_prfh_gather_scaled_sxtw_index_nx2vi64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: prfh pldl1strm, p0, [x0, z0.d, sxtw #1]
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; CHECK-NEXT: ret
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call void @llvm.aarch64.sve.prfh.gather.sxtw.index.nx2vi64(<vscale x 2 x i1> %Pg, ptr %base, <vscale x 2 x i32> %indexes, i32 1)
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ret void
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}
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; PRFH <prfop>, <Pg>, [<Xn|SP>, <Zm>.D] -> 64-bit indexes
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define void @llvm_aarch64_sve_prfh_gather_scaled_nx2vi64(<vscale x 2 x i1> %Pg, ptr %base, <vscale x 2 x i64> %indexes) nounwind {
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; CHECK-LABEL: llvm_aarch64_sve_prfh_gather_scaled_nx2vi64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: prfh pldl1strm, p0, [x0, z0.d, lsl #1]
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; CHECK-NEXT: ret
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call void @llvm.aarch64.sve.prfh.gather.index.nx2vi64(<vscale x 2 x i1> %Pg, ptr %base, <vscale x 2 x i64> %indexes, i32 1)
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ret void
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}
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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; PRFW <prfop>, <Pg>, [<Xn|SP>, <Zm>.S, <mod>] -> 32-bit indexes
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define void @llvm_aarch64_sve_prfw_gather_uxtw_index_nx4vi32(<vscale x 4 x i1> %Pg, ptr %base, <vscale x 4 x i32> %indexes) nounwind {
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; CHECK-LABEL: llvm_aarch64_sve_prfw_gather_uxtw_index_nx4vi32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: prfw pldl1strm, p0, [x0, z0.s, uxtw #2]
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; CHECK-NEXT: ret
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call void @llvm.aarch64.sve.prfw.gather.uxtw.index.nx4vi32(<vscale x 4 x i1> %Pg, ptr %base, <vscale x 4 x i32> %indexes, i32 1)
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ret void
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}
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define void @llvm_aarch64_sve_prfw_gather_scaled_sxtw_index_nx4vi32(<vscale x 4 x i1> %Pg, ptr %base, <vscale x 4 x i32> %indexes) nounwind {
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; CHECK-LABEL: llvm_aarch64_sve_prfw_gather_scaled_sxtw_index_nx4vi32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: prfw pldl1strm, p0, [x0, z0.s, sxtw #2]
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; CHECK-NEXT: ret
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call void @llvm.aarch64.sve.prfw.gather.sxtw.index.nx4vi32(<vscale x 4 x i1> %Pg, ptr %base, <vscale x 4 x i32> %indexes, i32 1)
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ret void
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}
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; PRFW <prfop>, <Pg>, [<Xn|SP>, <Zm>.D, <mod> #2] -> 32-bit unpacked indexes
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define void @llvm_aarch64_sve_prfw_gather_uxtw_index_nx2vi64(<vscale x 2 x i1> %Pg, ptr %base, <vscale x 2 x i32> %indexes) nounwind {
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; CHECK-LABEL: llvm_aarch64_sve_prfw_gather_uxtw_index_nx2vi64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: prfw pldl1strm, p0, [x0, z0.d, uxtw #2]
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; CHECK-NEXT: ret
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call void @llvm.aarch64.sve.prfw.gather.uxtw.index.nx2vi64(<vscale x 2 x i1> %Pg, ptr %base, <vscale x 2 x i32> %indexes, i32 1)
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ret void
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}
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define void @llvm_aarch64_sve_prfw_gather_scaled_sxtw_index_nx2vi64(<vscale x 2 x i1> %Pg, ptr %base, <vscale x 2 x i32> %indexes) nounwind {
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; CHECK-LABEL: llvm_aarch64_sve_prfw_gather_scaled_sxtw_index_nx2vi64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: prfw pldl1strm, p0, [x0, z0.d, sxtw #2]
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; CHECK-NEXT: ret
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call void @llvm.aarch64.sve.prfw.gather.sxtw.index.nx2vi64(<vscale x 2 x i1> %Pg, ptr %base, <vscale x 2 x i32> %indexes, i32 1)
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ret void
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}
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; PRFW <prfop>, <Pg>, [<Xn|SP>, <Zm>.D] -> 64-bit indexes
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define void @llvm_aarch64_sve_prfw_gather_scaled_nx2vi64(<vscale x 2 x i1> %Pg, ptr %base, <vscale x 2 x i64> %indexes) nounwind {
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; CHECK-LABEL: llvm_aarch64_sve_prfw_gather_scaled_nx2vi64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: prfw pldl1strm, p0, [x0, z0.d, lsl #2]
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; CHECK-NEXT: ret
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call void @llvm.aarch64.sve.prfw.gather.index.nx2vi64(<vscale x 2 x i1> %Pg, ptr %base, <vscale x 2 x i64> %indexes, i32 1)
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ret void
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}
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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; PRFD <prfop>, <Pg>, [<Xn|SP>, <Zm>.S, <mod>] -> 32-bit indexes
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define void @llvm_aarch64_sve_prfd_gather_uxtw_index_nx4vi32(<vscale x 4 x i1> %Pg, ptr %base, <vscale x 4 x i32> %indexes) nounwind {
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; CHECK-LABEL: llvm_aarch64_sve_prfd_gather_uxtw_index_nx4vi32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: prfd pldl1strm, p0, [x0, z0.s, uxtw #3]
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; CHECK-NEXT: ret
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call void @llvm.aarch64.sve.prfd.gather.uxtw.index.nx4vi32(<vscale x 4 x i1> %Pg, ptr %base, <vscale x 4 x i32> %indexes, i32 1)
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ret void
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}
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define void @llvm_aarch64_sve_prfd_gather_scaled_sxtw_index_nx4vi32(<vscale x 4 x i1> %Pg, ptr %base, <vscale x 4 x i32> %indexes) nounwind {
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; CHECK-LABEL: llvm_aarch64_sve_prfd_gather_scaled_sxtw_index_nx4vi32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: prfd pldl1strm, p0, [x0, z0.s, sxtw #3]
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; CHECK-NEXT: ret
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call void @llvm.aarch64.sve.prfd.gather.sxtw.index.nx4vi32(<vscale x 4 x i1> %Pg, ptr %base, <vscale x 4 x i32> %indexes, i32 1)
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ret void
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}
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; PRFD <prfop>, <Pg>, [<Xn|SP>, <Zm>.D, <mod> #3] -> 32-bit unpacked indexes
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define void @llvm_aarch64_sve_prfd_gather_uxtw_index_nx2vi64(<vscale x 2 x i1> %Pg, ptr %base, <vscale x 2 x i32> %indexes) nounwind {
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; CHECK-LABEL: llvm_aarch64_sve_prfd_gather_uxtw_index_nx2vi64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: prfd pldl1strm, p0, [x0, z0.d, uxtw #3]
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; CHECK-NEXT: ret
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call void @llvm.aarch64.sve.prfd.gather.uxtw.index.nx2vi64(<vscale x 2 x i1> %Pg, ptr %base, <vscale x 2 x i32> %indexes, i32 1)
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ret void
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}
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define void @llvm_aarch64_sve_prfd_gather_scaled_sxtw_index_nx2vi64(<vscale x 2 x i1> %Pg, ptr %base, <vscale x 2 x i32> %indexes) nounwind {
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; CHECK-LABEL: llvm_aarch64_sve_prfd_gather_scaled_sxtw_index_nx2vi64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: prfd pldl1strm, p0, [x0, z0.d, sxtw #3]
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; CHECK-NEXT: ret
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call void @llvm.aarch64.sve.prfd.gather.sxtw.index.nx2vi64(<vscale x 2 x i1> %Pg, ptr %base, <vscale x 2 x i32> %indexes, i32 1)
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ret void
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}
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; PRFD <prfop>, <Pg>, [<Xn|SP>, <Zm>.D] -> 64-bit indexes
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define void @llvm_aarch64_sve_prfd_gather_scaled_nx2vi64(<vscale x 2 x i1> %Pg, ptr %base, <vscale x 2 x i64> %indexes) nounwind {
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; CHECK-LABEL: llvm_aarch64_sve_prfd_gather_scaled_nx2vi64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: prfd pldl1strm, p0, [x0, z0.d, lsl #3]
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; CHECK-NEXT: ret
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call void @llvm.aarch64.sve.prfd.gather.index.nx2vi64(<vscale x 2 x i1> %Pg, ptr %base, <vscale x 2 x i64> %indexes, i32 1)
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ret void
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}
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declare void @llvm.aarch64.sve.prfb.gather.sxtw.index.nx4vi32(<vscale x 4 x i1> %Pg, ptr %base, <vscale x 4 x i32> %indexes, i32 %prfop)
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declare void @llvm.aarch64.sve.prfb.gather.uxtw.index.nx4vi32(<vscale x 4 x i1> %Pg, ptr %base, <vscale x 4 x i32> %indexes, i32 %prfop)
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declare void @llvm.aarch64.sve.prfb.gather.sxtw.index.nx2vi64(<vscale x 2 x i1> %Pg, ptr %base, <vscale x 2 x i32> %indexes, i32 %prfop)
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declare void @llvm.aarch64.sve.prfb.gather.uxtw.index.nx2vi64(<vscale x 2 x i1> %Pg, ptr %base, <vscale x 2 x i32> %indexes, i32 %prfop)
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declare void @llvm.aarch64.sve.prfb.gather.index.nx2vi64(<vscale x 2 x i1> %Pg, ptr %base, <vscale x 2 x i64> %indexes, i32 %prfop)
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declare void @llvm.aarch64.sve.prfh.gather.sxtw.index.nx4vi32(<vscale x 4 x i1> %Pg, ptr %base, <vscale x 4 x i32> %indexes, i32 %prfop)
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declare void @llvm.aarch64.sve.prfh.gather.uxtw.index.nx4vi32(<vscale x 4 x i1> %Pg, ptr %base, <vscale x 4 x i32> %indexes, i32 %prfop)
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declare void @llvm.aarch64.sve.prfh.gather.sxtw.index.nx2vi64(<vscale x 2 x i1> %Pg, ptr %base, <vscale x 2 x i32> %indexes, i32 %prfop)
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declare void @llvm.aarch64.sve.prfh.gather.uxtw.index.nx2vi64(<vscale x 2 x i1> %Pg, ptr %base, <vscale x 2 x i32> %indexes, i32 %prfop)
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declare void @llvm.aarch64.sve.prfh.gather.index.nx2vi64(<vscale x 2 x i1> %Pg, ptr %base, <vscale x 2 x i64> %indexes, i32 %prfop)
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declare void @llvm.aarch64.sve.prfw.gather.sxtw.index.nx4vi32(<vscale x 4 x i1> %Pg, ptr %base, <vscale x 4 x i32> %indexes, i32 %prfop)
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declare void @llvm.aarch64.sve.prfw.gather.uxtw.index.nx4vi32(<vscale x 4 x i1> %Pg, ptr %base, <vscale x 4 x i32> %indexes, i32 %prfop)
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declare void @llvm.aarch64.sve.prfw.gather.sxtw.index.nx2vi64(<vscale x 2 x i1> %Pg, ptr %base, <vscale x 2 x i32> %indexes, i32 %prfop)
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declare void @llvm.aarch64.sve.prfw.gather.uxtw.index.nx2vi64(<vscale x 2 x i1> %Pg, ptr %base, <vscale x 2 x i32> %indexes, i32 %prfop)
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declare void @llvm.aarch64.sve.prfw.gather.index.nx2vi64(<vscale x 2 x i1> %Pg, ptr %base, <vscale x 2 x i64> %indexes, i32 %prfop)
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declare void @llvm.aarch64.sve.prfd.gather.sxtw.index.nx4vi32(<vscale x 4 x i1> %Pg, ptr %base, <vscale x 4 x i32> %indexes, i32 %prfop)
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declare void @llvm.aarch64.sve.prfd.gather.uxtw.index.nx4vi32(<vscale x 4 x i1> %Pg, ptr %base, <vscale x 4 x i32> %indexes, i32 %prfop)
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declare void @llvm.aarch64.sve.prfd.gather.sxtw.index.nx2vi64(<vscale x 2 x i1> %Pg, ptr %base, <vscale x 2 x i32> %indexes, i32 %prfop)
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declare void @llvm.aarch64.sve.prfd.gather.uxtw.index.nx2vi64(<vscale x 2 x i1> %Pg, ptr %base, <vscale x 2 x i32> %indexes, i32 %prfop)
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declare void @llvm.aarch64.sve.prfd.gather.index.nx2vi64(<vscale x 2 x i1> %Pg, ptr %base, <vscale x 2 x i64> %indexes, i32 %prfop)
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