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43 lines
1.9 KiB
YAML
43 lines
1.9 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=aarch64 -mattr=+sve -mattr=+use-experimental-zeroing-pseudos -run-pass=aarch64-expand-pseudo %s -o - | FileCheck %s
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# RUN: llc -mtriple=aarch64 -mattr=+sve -mattr=+use-experimental-zeroing-pseudos -passes=aarch64-expand-pseudo %s -o - | FileCheck %s
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# Should create an additional LSL to zero the lanes as the DstReg is not unique
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--- |
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define <vscale x 4 x float> @fsub_s_zero(<vscale x 4 x i1> %pg, <vscale x 4 x float> %a){
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%a_z = select <vscale x 4 x i1> %pg, <vscale x 4 x float> %a, <vscale x 4 x float> zeroinitializer
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%out = call <vscale x 4 x float> @llvm.aarch64.sve.fsub.nxv4f32(<vscale x 4 x i1> %pg,
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<vscale x 4 x float> %a_z,
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<vscale x 4 x float> %a_z)
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ret <vscale x 4 x float> %out
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}
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declare <vscale x 4 x float> @llvm.aarch64.sve.fsub.nxv4f32(<vscale x 4 x i1>, <vscale x 4 x float>, <vscale x 4 x float>)
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...
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---
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name: fsub_s_zero
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alignment: 4
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tracksRegLiveness: true
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tracksDebugUserValues: true
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registers: []
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liveins:
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- { reg: '$p0', virtual-reg: '' }
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- { reg: '$z0', virtual-reg: '' }
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body: |
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bb.0 (%ir-block.0):
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liveins: $p0, $z0
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; CHECK-LABEL: name: fsub_s_zero
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; CHECK: liveins: $p0, $z0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: BUNDLE implicit-def $z0, implicit $p0, implicit $z0 {
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; CHECK-NEXT: $z0 = MOVPRFX_ZPzZ_S $p0, $z0
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; CHECK-NEXT: $z0 = LSL_ZPmI_S renamable $p0, internal $z0, 0
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; CHECK-NEXT: $z0 = FSUBR_ZPmZ_S renamable $p0, internal killed $z0, internal killed renamable $z0
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; CHECK-NEXT: }
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; CHECK-NEXT: RET undef $lr, implicit $z0
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renamable $z0 = nnan ninf nsz arcp contract afn reassoc FSUB_ZPZZ_S_ZERO renamable $p0, killed renamable $z0, renamable $z0
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RET_ReallyLR implicit $z0
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...
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