derek.holloway
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93 lines
3.1 KiB
LLVM
93 lines
3.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve,+f64mm < %s | FileCheck %s
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;
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; LD1ROB
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;
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define <vscale x 16 x i8> @ld1rob_i8(<vscale x 16 x i1> %pred, ptr %addr) nounwind {
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; CHECK-LABEL: ld1rob_i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ld1rob { z0.b }, p0/z, [x0]
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; CHECK-NEXT: ret
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%res = call <vscale x 16 x i8> @llvm.aarch64.sve.ld1ro.nxv16i8(<vscale x 16 x i1> %pred, ptr %addr)
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ret <vscale x 16 x i8> %res
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}
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;
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; LD1ROH
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;
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define <vscale x 8 x i16> @ld1roh_i16(<vscale x 8 x i1> %pred, ptr %addr) nounwind {
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; CHECK-LABEL: ld1roh_i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ld1roh { z0.h }, p0/z, [x0]
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; CHECK-NEXT: ret
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%res = call <vscale x 8 x i16> @llvm.aarch64.sve.ld1ro.nxv8i16(<vscale x 8 x i1> %pred, ptr %addr)
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ret <vscale x 8 x i16> %res
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}
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define <vscale x 8 x half> @ld1roh_half(<vscale x 8 x i1> %pred, ptr %addr) nounwind {
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; CHECK-LABEL: ld1roh_half:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ld1roh { z0.h }, p0/z, [x0]
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; CHECK-NEXT: ret
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%res = call <vscale x 8 x half> @llvm.aarch64.sve.ld1ro.nxv8f16(<vscale x 8 x i1> %pred, ptr %addr)
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ret <vscale x 8 x half> %res
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}
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;
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; LD1ROW
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;
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define <vscale x 4 x i32> @ld1row_i32(<vscale x 4 x i1> %pred, ptr %addr) nounwind {
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; CHECK-LABEL: ld1row_i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ld1row { z0.s }, p0/z, [x0]
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; CHECK-NEXT: ret
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%res = call <vscale x 4 x i32> @llvm.aarch64.sve.ld1ro.nxv4i32(<vscale x 4 x i1> %pred, ptr %addr)
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ret <vscale x 4 x i32> %res
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}
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define <vscale x 4 x float> @ld1row_float(<vscale x 4 x i1> %pred, ptr %addr) nounwind {
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; CHECK-LABEL: ld1row_float:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ld1row { z0.s }, p0/z, [x0]
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; CHECK-NEXT: ret
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%res = call <vscale x 4 x float> @llvm.aarch64.sve.ld1ro.nxv4f32(<vscale x 4 x i1> %pred, ptr %addr)
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ret <vscale x 4 x float> %res
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}
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;
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; LD1ROD
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;
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define <vscale x 2 x i64> @ld1rod_i64(<vscale x 2 x i1> %pred, ptr %addr) nounwind {
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; CHECK-LABEL: ld1rod_i64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ld1rod { z0.d }, p0/z, [x0]
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; CHECK-NEXT: ret
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%res = call <vscale x 2 x i64> @llvm.aarch64.sve.ld1ro.nxv2i64(<vscale x 2 x i1> %pred, ptr %addr)
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ret <vscale x 2 x i64> %res
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}
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define <vscale x 2 x double> @ld1rod_double(<vscale x 2 x i1> %pred, ptr %addr) nounwind {
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; CHECK-LABEL: ld1rod_double:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ld1rod { z0.d }, p0/z, [x0]
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; CHECK-NEXT: ret
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%res = call <vscale x 2 x double> @llvm.aarch64.sve.ld1ro.nxv2f64(<vscale x 2 x i1> %pred, ptr %addr)
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ret <vscale x 2 x double> %res
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}
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declare <vscale x 16 x i8> @llvm.aarch64.sve.ld1ro.nxv16i8(<vscale x 16 x i1>, ptr)
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declare <vscale x 8 x i16> @llvm.aarch64.sve.ld1ro.nxv8i16(<vscale x 8 x i1>, ptr)
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declare <vscale x 8 x half> @llvm.aarch64.sve.ld1ro.nxv8f16(<vscale x 8 x i1>, ptr)
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declare <vscale x 4 x i32> @llvm.aarch64.sve.ld1ro.nxv4i32(<vscale x 4 x i1>, ptr)
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declare <vscale x 4 x float> @llvm.aarch64.sve.ld1ro.nxv4f32(<vscale x 4 x i1>, ptr)
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declare <vscale x 2 x i64> @llvm.aarch64.sve.ld1ro.nxv2i64(<vscale x 2 x i1>, ptr)
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declare <vscale x 2 x double> @llvm.aarch64.sve.ld1ro.nxv2f64(<vscale x 2 x i1>, ptr)
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