derek.holloway
7502bf64a4
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238 lines
14 KiB
LLVM
238 lines
14 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc -mtriple aarch64 -mattr=+sve2 -o - %s | FileCheck %s
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define void @test(ptr nocapture noundef readonly %kernel, i32 noundef %kw, float noundef nofpclass(nan inf) %kernel_factor, ptr %call5.i.i.i119) vscale_range(1, 16) {
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; CHECK-LABEL: test:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: cmp w1, #1
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; CHECK-NEXT: b.lt .LBB0_6
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; CHECK-NEXT: // %bb.1: // %for.body.lr.ph
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; CHECK-NEXT: rdvl x8, #-2
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; CHECK-NEXT: mov w9, #608 // =0x260
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; CHECK-NEXT: ands x11, x8, x9
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; CHECK-NEXT: b.eq .LBB0_6
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; CHECK-NEXT: // %bb.2: // %for.body.us.preheader
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; CHECK-NEXT: ptrue p0.h
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; CHECK-NEXT: add x11, x2, x11, lsl #1
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; CHECK-NEXT: mov w8, wzr
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; CHECK-NEXT: ptrue p1.b
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; CHECK-NEXT: mov x9, xzr
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; CHECK-NEXT: mov w10, wzr
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; CHECK-NEXT: mov x12, #4 // =0x4
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; CHECK-NEXT: mov x13, #8 // =0x8
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; CHECK-NEXT: .LBB0_3: // %for.body.us
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; CHECK-NEXT: // =>This Loop Header: Depth=1
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; CHECK-NEXT: // Child Loop BB0_4 Depth 2
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; CHECK-NEXT: add x14, x0, x9, lsl #2
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; CHECK-NEXT: sbfiz x15, x8, #1, #32
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; CHECK-NEXT: mov x16, x2
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; CHECK-NEXT: ldp s0, s1, [x14]
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; CHECK-NEXT: add x15, x15, #8
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; CHECK-NEXT: ldp s2, s3, [x14, #8]
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; CHECK-NEXT: ubfiz x14, x8, #1, #32
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; CHECK-NEXT: fcvt h0, s0
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; CHECK-NEXT: fcvt h1, s1
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; CHECK-NEXT: fcvt h2, s2
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; CHECK-NEXT: fcvt h3, s3
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; CHECK-NEXT: mov z0.h, h0
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; CHECK-NEXT: mov z1.h, h1
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; CHECK-NEXT: mov z2.h, h2
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; CHECK-NEXT: mov z3.h, h3
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; CHECK-NEXT: .LBB0_4: // %for.cond.i.preheader.us
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; CHECK-NEXT: // Parent Loop BB0_3 Depth=1
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; CHECK-NEXT: // => This Inner Loop Header: Depth=2
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; CHECK-NEXT: ld1b { z4.b }, p1/z, [x16, x14]
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; CHECK-NEXT: ldr z5, [x16]
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; CHECK-NEXT: add x17, x16, x15
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; CHECK-NEXT: add x18, x16, x14
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; CHECK-NEXT: add x3, x17, #8
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; CHECK-NEXT: add x4, x17, #16
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; CHECK-NEXT: fmad z4.h, p0/m, z0.h, z5.h
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; CHECK-NEXT: ld1b { z5.b }, p1/z, [x16, x15]
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; CHECK-NEXT: fmla z4.h, p0/m, z5.h, z1.h
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; CHECK-NEXT: ld1h { z5.h }, p0/z, [x17, x12, lsl #1]
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; CHECK-NEXT: fmla z4.h, p0/m, z5.h, z2.h
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; CHECK-NEXT: ld1h { z5.h }, p0/z, [x17, x13, lsl #1]
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; CHECK-NEXT: fmla z4.h, p0/m, z5.h, z3.h
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; CHECK-NEXT: ldr z5, [x16, #1, mul vl]
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; CHECK-NEXT: str z4, [x16]
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; CHECK-NEXT: ldr z4, [x18, #1, mul vl]
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; CHECK-NEXT: fmad z4.h, p0/m, z0.h, z5.h
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; CHECK-NEXT: ldr z5, [x17, #1, mul vl]
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; CHECK-NEXT: fmla z4.h, p0/m, z5.h, z1.h
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; CHECK-NEXT: ldr z5, [x3, #1, mul vl]
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; CHECK-NEXT: fmla z4.h, p0/m, z5.h, z2.h
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; CHECK-NEXT: ldr z5, [x4, #1, mul vl]
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; CHECK-NEXT: fmla z4.h, p0/m, z5.h, z3.h
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; CHECK-NEXT: ldr z5, [x16, #2, mul vl]
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; CHECK-NEXT: str z4, [x16, #1, mul vl]
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; CHECK-NEXT: ldr z4, [x18, #2, mul vl]
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; CHECK-NEXT: fmad z4.h, p0/m, z0.h, z5.h
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; CHECK-NEXT: ldr z5, [x17, #2, mul vl]
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; CHECK-NEXT: fmla z4.h, p0/m, z5.h, z1.h
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; CHECK-NEXT: ldr z5, [x3, #2, mul vl]
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; CHECK-NEXT: fmla z4.h, p0/m, z5.h, z2.h
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; CHECK-NEXT: ldr z5, [x4, #2, mul vl]
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; CHECK-NEXT: fmla z4.h, p0/m, z5.h, z3.h
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; CHECK-NEXT: ldr z5, [x16, #3, mul vl]
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; CHECK-NEXT: str z4, [x16, #2, mul vl]
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; CHECK-NEXT: ldr z4, [x18, #3, mul vl]
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; CHECK-NEXT: fmad z4.h, p0/m, z0.h, z5.h
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; CHECK-NEXT: ldr z5, [x17, #3, mul vl]
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; CHECK-NEXT: fmla z4.h, p0/m, z5.h, z1.h
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; CHECK-NEXT: ldr z5, [x3, #3, mul vl]
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; CHECK-NEXT: fmla z4.h, p0/m, z5.h, z2.h
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; CHECK-NEXT: ldr z5, [x4, #3, mul vl]
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; CHECK-NEXT: fmla z4.h, p0/m, z5.h, z3.h
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; CHECK-NEXT: str z4, [x16, #3, mul vl]
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; CHECK-NEXT: incb x16, all, mul #4
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; CHECK-NEXT: cmp x16, x11
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; CHECK-NEXT: b.lo .LBB0_4
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; CHECK-NEXT: // %bb.5: // %while.cond.i..exit_crit_edge.us
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; CHECK-NEXT: // in Loop: Header=BB0_3 Depth=1
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; CHECK-NEXT: add w10, w10, #1
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; CHECK-NEXT: add x9, x9, #4
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; CHECK-NEXT: add w8, w8, #16
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; CHECK-NEXT: cmp w10, w1
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; CHECK-NEXT: b.ne .LBB0_3
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; CHECK-NEXT: .LBB0_6: // %exit78
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; CHECK-NEXT: ret
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entry:
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;%call5.i.i.i119 = tail call noalias noundef nonnull dereferenceable(1248) ptr @_Znwm(i64 noundef 1248) #7
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%cmp139 = icmp sgt i32 %kw, 0
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;tail call void @llvm.memset.p0.i64(ptr noundef nonnull align 2 dereferenceable(1248) %call5.i.i.i119, i8 0, i64 1248, i1 false)
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br i1 %cmp139, label %for.body.lr.ph, label %exit78
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for.body.lr.ph: ; preds = %entry
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%0 = tail call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31)
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%vscale = tail call i64 @llvm.vscale.i64()
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%mul5.i = shl nuw nsw i64 %vscale, 5
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%sub.not.i = sub nsw i64 0, %mul5.i
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%sub6.i = and i64 %sub.not.i, 608
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%add.ptr.i = getelementptr inbounds half, ptr %call5.i.i.i119, i64 %sub6.i
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%cmp.i133.not = icmp eq i64 %sub6.i, 0
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%vs2 = shl nuw nsw i64 %vscale, 4
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br i1 %cmp.i133.not, label %exit78, label %for.body.us.preheader
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for.body.us.preheader: ; preds = %for.body.lr.ph
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%.idx.i.us.2 = shl nuw nsw i64 %vscale, 5
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%.idx.i.us.3 = mul nuw nsw i64 %vscale, 48
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br label %for.body.us
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for.body.us: ; preds = %for.body.us.preheader, %while.cond.i..exit_crit_edge.us
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%indvars.iv = phi i64 [ 0, %for.body.us.preheader ], [ %indvars.iv.next, %while.cond.i..exit_crit_edge.us ]
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%i4.0140.us = phi i32 [ 0, %for.body.us.preheader ], [ %inc.us, %while.cond.i..exit_crit_edge.us ]
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%3 = trunc nuw nsw i64 %indvars.iv to i32
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%mul6.us = shl i32 %3, 2
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%idx.ext.us = zext nneg i32 %mul6.us to i64
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%add.ptr.us = getelementptr inbounds half, ptr %call5.i.i.i119, i64 %idx.ext.us
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%mul11.us = or disjoint i32 %mul6.us, 4
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%idx.ext12.us = sext i32 %mul11.us to i64
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%add.ptr13.us = getelementptr inbounds half, ptr %call5.i.i.i119, i64 %idx.ext12.us
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%mul18.us = or disjoint i32 %mul6.us, 8
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%idx.ext19.us = sext i32 %mul18.us to i64
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%add.ptr20.us = getelementptr inbounds half, ptr %call5.i.i.i119, i64 %idx.ext19.us
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%mul25.us = or disjoint i32 %mul6.us, 12
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%idx.ext26.us = sext i32 %mul25.us to i64
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%add.ptr27.us = getelementptr inbounds half, ptr %call5.i.i.i119, i64 %idx.ext26.us
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%add.ptr29.us = getelementptr inbounds float, ptr %kernel, i64 %indvars.iv
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%4 = load float, ptr %add.ptr29.us, align 4
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%5 = fptrunc float %4 to half
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%.splatinsert.i.us = insertelement <vscale x 8 x half> poison, half %5, i64 0
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%6 = shufflevector <vscale x 8 x half> %.splatinsert.i.us, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
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%arrayidx2.i.us = getelementptr inbounds i8, ptr %add.ptr29.us, i64 4
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%7 = load float, ptr %arrayidx2.i.us, align 4
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%8 = fptrunc float %7 to half
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%.splatinsert57.i.us = insertelement <vscale x 8 x half> poison, half %8, i64 0
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%9 = shufflevector <vscale x 8 x half> %.splatinsert57.i.us, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
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%arrayidx3.i.us = getelementptr inbounds i8, ptr %add.ptr29.us, i64 8
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%10 = load float, ptr %arrayidx3.i.us, align 4
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%11 = fptrunc float %10 to half
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%.splatinsert58.i.us = insertelement <vscale x 8 x half> poison, half %11, i64 0
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%12 = shufflevector <vscale x 8 x half> %.splatinsert58.i.us, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
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%arrayidx4.i.us = getelementptr inbounds i8, ptr %add.ptr29.us, i64 12
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%13 = load float, ptr %arrayidx4.i.us, align 4
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%14 = fptrunc float %13 to half
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%.splatinsert59.i.us = insertelement <vscale x 8 x half> poison, half %14, i64 0
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%15 = shufflevector <vscale x 8 x half> %.splatinsert59.i.us, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
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br label %for.cond.i.preheader.us
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for.cond.i.preheader.us: ; preds = %for.body.us, %for.cond.i.preheader.us
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%vdst.0.i138.us = phi ptr [ %call5.i.i.i119, %for.body.us ], [ %add.ptr15.i.us, %for.cond.i.preheader.us ]
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%s1.0.i137.us = phi ptr [ %add.ptr.us, %for.body.us ], [ %add.ptr16.i.us, %for.cond.i.preheader.us ]
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%s2.0.i136.us = phi ptr [ %add.ptr13.us, %for.body.us ], [ %add.ptr17.i.us, %for.cond.i.preheader.us ]
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%s3.0.i135.us = phi ptr [ %add.ptr20.us, %for.body.us ], [ %add.ptr18.i.us, %for.cond.i.preheader.us ]
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%s4.0.i134.us = phi ptr [ %add.ptr27.us, %for.body.us ], [ %add.ptr19.i.us, %for.cond.i.preheader.us ]
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%16 = load <vscale x 8 x half>, ptr %s1.0.i137.us, align 16
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%17 = load <vscale x 8 x half>, ptr %vdst.0.i138.us, align 16
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%18 = tail call fast <vscale x 8 x half> @llvm.aarch64.sve.fmla.u.nxv8f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %17, <vscale x 8 x half> %16, <vscale x 8 x half> %6)
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%19 = load <vscale x 8 x half>, ptr %s2.0.i136.us, align 16
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%20 = tail call fast <vscale x 8 x half> @llvm.aarch64.sve.fmla.u.nxv8f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %18, <vscale x 8 x half> %19, <vscale x 8 x half> %9)
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%21 = load <vscale x 8 x half>, ptr %s3.0.i135.us, align 16
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%22 = tail call fast <vscale x 8 x half> @llvm.aarch64.sve.fmla.u.nxv8f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %20, <vscale x 8 x half> %21, <vscale x 8 x half> %12)
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%23 = load <vscale x 8 x half>, ptr %s4.0.i134.us, align 16
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%24 = tail call fast <vscale x 8 x half> @llvm.aarch64.sve.fmla.u.nxv8f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %22, <vscale x 8 x half> %23, <vscale x 8 x half> %15)
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store <vscale x 8 x half> %24, ptr %vdst.0.i138.us, align 16
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%25 = getelementptr i8, ptr %s1.0.i137.us, i64 %vs2
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%26 = load <vscale x 8 x half>, ptr %25, align 16
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%27 = getelementptr i8, ptr %vdst.0.i138.us, i64 %vs2
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%28 = load <vscale x 8 x half>, ptr %27, align 16
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%29 = tail call fast <vscale x 8 x half> @llvm.aarch64.sve.fmla.u.nxv8f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %28, <vscale x 8 x half> %26, <vscale x 8 x half> %6)
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%30 = getelementptr i8, ptr %s2.0.i136.us, i64 %vs2
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%31 = load <vscale x 8 x half>, ptr %30, align 16
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%32 = tail call fast <vscale x 8 x half> @llvm.aarch64.sve.fmla.u.nxv8f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %29, <vscale x 8 x half> %31, <vscale x 8 x half> %9)
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%33 = getelementptr i8, ptr %s3.0.i135.us, i64 %vs2
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%34 = load <vscale x 8 x half>, ptr %33, align 16
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%35 = tail call fast <vscale x 8 x half> @llvm.aarch64.sve.fmla.u.nxv8f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %32, <vscale x 8 x half> %34, <vscale x 8 x half> %12)
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%36 = getelementptr i8, ptr %s4.0.i134.us, i64 %vs2
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%37 = load <vscale x 8 x half>, ptr %36, align 16
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%38 = tail call fast <vscale x 8 x half> @llvm.aarch64.sve.fmla.u.nxv8f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %35, <vscale x 8 x half> %37, <vscale x 8 x half> %15)
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store <vscale x 8 x half> %38, ptr %27, align 16
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%39 = getelementptr i8, ptr %s1.0.i137.us, i64 %.idx.i.us.2
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%40 = load <vscale x 8 x half>, ptr %39, align 16
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%41 = getelementptr i8, ptr %vdst.0.i138.us, i64 %.idx.i.us.2
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%42 = load <vscale x 8 x half>, ptr %41, align 16
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%43 = tail call fast <vscale x 8 x half> @llvm.aarch64.sve.fmla.u.nxv8f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %42, <vscale x 8 x half> %40, <vscale x 8 x half> %6)
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%44 = getelementptr i8, ptr %s2.0.i136.us, i64 %.idx.i.us.2
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%45 = load <vscale x 8 x half>, ptr %44, align 16
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%46 = tail call fast <vscale x 8 x half> @llvm.aarch64.sve.fmla.u.nxv8f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %43, <vscale x 8 x half> %45, <vscale x 8 x half> %9)
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%47 = getelementptr i8, ptr %s3.0.i135.us, i64 %.idx.i.us.2
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%48 = load <vscale x 8 x half>, ptr %47, align 16
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%49 = tail call fast <vscale x 8 x half> @llvm.aarch64.sve.fmla.u.nxv8f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %46, <vscale x 8 x half> %48, <vscale x 8 x half> %12)
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%50 = getelementptr i8, ptr %s4.0.i134.us, i64 %.idx.i.us.2
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%51 = load <vscale x 8 x half>, ptr %50, align 16
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%52 = tail call fast <vscale x 8 x half> @llvm.aarch64.sve.fmla.u.nxv8f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %49, <vscale x 8 x half> %51, <vscale x 8 x half> %15)
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store <vscale x 8 x half> %52, ptr %41, align 16
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%53 = getelementptr i8, ptr %s1.0.i137.us, i64 %.idx.i.us.3
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%54 = load <vscale x 8 x half>, ptr %53, align 16
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%55 = getelementptr i8, ptr %vdst.0.i138.us, i64 %.idx.i.us.3
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%56 = load <vscale x 8 x half>, ptr %55, align 16
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%57 = tail call fast <vscale x 8 x half> @llvm.aarch64.sve.fmla.u.nxv8f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %56, <vscale x 8 x half> %54, <vscale x 8 x half> %6)
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%58 = getelementptr i8, ptr %s2.0.i136.us, i64 %.idx.i.us.3
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%59 = load <vscale x 8 x half>, ptr %58, align 16
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%60 = tail call fast <vscale x 8 x half> @llvm.aarch64.sve.fmla.u.nxv8f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %57, <vscale x 8 x half> %59, <vscale x 8 x half> %9)
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%61 = getelementptr i8, ptr %s3.0.i135.us, i64 %.idx.i.us.3
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%62 = load <vscale x 8 x half>, ptr %61, align 16
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%63 = tail call fast <vscale x 8 x half> @llvm.aarch64.sve.fmla.u.nxv8f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %60, <vscale x 8 x half> %62, <vscale x 8 x half> %12)
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%64 = getelementptr i8, ptr %s4.0.i134.us, i64 %.idx.i.us.3
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%65 = load <vscale x 8 x half>, ptr %64, align 16
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%66 = tail call fast <vscale x 8 x half> @llvm.aarch64.sve.fmla.u.nxv8f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %63, <vscale x 8 x half> %65, <vscale x 8 x half> %15)
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store <vscale x 8 x half> %66, ptr %55, align 16
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%add.ptr15.i.us = getelementptr inbounds half, ptr %vdst.0.i138.us, i64 %mul5.i
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%add.ptr16.i.us = getelementptr inbounds half, ptr %s1.0.i137.us, i64 %mul5.i
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%add.ptr17.i.us = getelementptr inbounds half, ptr %s2.0.i136.us, i64 %mul5.i
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%add.ptr18.i.us = getelementptr inbounds half, ptr %s3.0.i135.us, i64 %mul5.i
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%add.ptr19.i.us = getelementptr inbounds half, ptr %s4.0.i134.us, i64 %mul5.i
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%cmp.i.us = icmp ult ptr %add.ptr15.i.us, %add.ptr.i
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br i1 %cmp.i.us, label %for.cond.i.preheader.us, label %while.cond.i..exit_crit_edge.us
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while.cond.i..exit_crit_edge.us: ; preds = %for.cond.i.preheader.us
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%indvars.iv.next = add nuw nsw i64 %indvars.iv, 4
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%inc.us = add nuw nsw i32 %i4.0140.us, 1
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%exitcond.not = icmp eq i32 %inc.us, %kw
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br i1 %exitcond.not, label %exit78, label %for.body.us
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exit78: ; preds = %while.cond.i..exit_crit_edge.us, %for.body.lr.ph, %entry
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ret void
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}
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