derek.holloway
7502bf64a4
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187 lines
7.4 KiB
LLVM
187 lines
7.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=aarch64--linux-gnu -mattr=+sve < %s | FileCheck %s
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;
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; Masked Additions
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;
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define <vscale x 16 x i8> @masked_add_nxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, <vscale x 16 x i1> %mask) {
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; CHECK-LABEL: masked_add_nxv16i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: add z0.b, p0/m, z0.b, z1.b
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; CHECK-NEXT: ret
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%select = select <vscale x 16 x i1> %mask, <vscale x 16 x i8> %b, <vscale x 16 x i8> zeroinitializer
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%ret = add <vscale x 16 x i8> %a, %select
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ret <vscale x 16 x i8> %ret
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}
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define <vscale x 8 x i16> @masked_add_nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b, <vscale x 8 x i1> %mask) {
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; CHECK-LABEL: masked_add_nxv8i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: add z0.h, p0/m, z0.h, z1.h
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; CHECK-NEXT: ret
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%select = select <vscale x 8 x i1> %mask, <vscale x 8 x i16> %b, <vscale x 8 x i16> zeroinitializer
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%ret = add <vscale x 8 x i16> %a, %select
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ret <vscale x 8 x i16> %ret
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}
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define <vscale x 4 x i32> @masked_add_nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, <vscale x 4 x i1> %mask) {
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; CHECK-LABEL: masked_add_nxv4i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: add z0.s, p0/m, z0.s, z1.s
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; CHECK-NEXT: ret
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%select = select <vscale x 4 x i1> %mask, <vscale x 4 x i32> %b, <vscale x 4 x i32> zeroinitializer
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%ret = add <vscale x 4 x i32> %a, %select
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ret <vscale x 4 x i32> %ret
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}
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define <vscale x 2 x i64> @masked_add_nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b, <vscale x 2 x i1> %mask) {
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; CHECK-LABEL: masked_add_nxv2i64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: add z0.d, p0/m, z0.d, z1.d
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; CHECK-NEXT: ret
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%select = select <vscale x 2 x i1> %mask, <vscale x 2 x i64> %b, <vscale x 2 x i64> zeroinitializer
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%ret = add <vscale x 2 x i64> %a, %select
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ret <vscale x 2 x i64> %ret
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}
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;
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; Masked Subtractions
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;
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define <vscale x 16 x i8> @masked_sub_nxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, <vscale x 16 x i1> %mask) {
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; CHECK-LABEL: masked_sub_nxv16i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: sub z0.b, p0/m, z0.b, z1.b
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; CHECK-NEXT: ret
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%select = select <vscale x 16 x i1> %mask, <vscale x 16 x i8> %b, <vscale x 16 x i8> zeroinitializer
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%ret = sub <vscale x 16 x i8> %a, %select
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ret <vscale x 16 x i8> %ret
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}
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define <vscale x 8 x i16> @masked_sub_nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b, <vscale x 8 x i1> %mask) {
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; CHECK-LABEL: masked_sub_nxv8i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: sub z0.h, p0/m, z0.h, z1.h
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; CHECK-NEXT: ret
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%select = select <vscale x 8 x i1> %mask, <vscale x 8 x i16> %b, <vscale x 8 x i16> zeroinitializer
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%ret = sub <vscale x 8 x i16> %a, %select
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ret <vscale x 8 x i16> %ret
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}
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define <vscale x 4 x i32> @masked_sub_nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, <vscale x 4 x i1> %mask) {
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; CHECK-LABEL: masked_sub_nxv4i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: sub z0.s, p0/m, z0.s, z1.s
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; CHECK-NEXT: ret
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%select = select <vscale x 4 x i1> %mask, <vscale x 4 x i32> %b, <vscale x 4 x i32> zeroinitializer
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%ret = sub <vscale x 4 x i32> %a, %select
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ret <vscale x 4 x i32> %ret
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}
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define <vscale x 2 x i64> @masked_sub_nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b, <vscale x 2 x i1> %mask) {
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; CHECK-LABEL: masked_sub_nxv2i64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: sub z0.d, p0/m, z0.d, z1.d
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; CHECK-NEXT: ret
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%select = select <vscale x 2 x i1> %mask, <vscale x 2 x i64> %b, <vscale x 2 x i64> zeroinitializer
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%ret = sub <vscale x 2 x i64> %a, %select
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ret <vscale x 2 x i64> %ret
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}
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;
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; Masked multiply-add
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;
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define <vscale x 16 x i8> @masked_mla_nxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c, <vscale x 16 x i1> %mask) {
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; CHECK-LABEL: masked_mla_nxv16i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mla z0.b, p0/m, z1.b, z2.b
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; CHECK-NEXT: ret
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%mul = mul nsw <vscale x 16 x i8> %b, %c
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%sel = select <vscale x 16 x i1> %mask, <vscale x 16 x i8> %mul, <vscale x 16 x i8> zeroinitializer
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%add = add <vscale x 16 x i8> %a, %sel
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ret <vscale x 16 x i8> %add
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}
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define <vscale x 8 x i16> @masked_mla_nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b, <vscale x 8 x i16> %c, <vscale x 8 x i1> %mask) {
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; CHECK-LABEL: masked_mla_nxv8i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mla z0.h, p0/m, z1.h, z2.h
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; CHECK-NEXT: ret
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%mul = mul nsw <vscale x 8 x i16> %b, %c
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%sel = select <vscale x 8 x i1> %mask, <vscale x 8 x i16> %mul, <vscale x 8 x i16> zeroinitializer
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%add = add <vscale x 8 x i16> %a, %sel
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ret <vscale x 8 x i16> %add
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}
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define <vscale x 4 x i32> @masked_mla_nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, <vscale x 4 x i32> %c, <vscale x 4 x i1> %mask) {
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; CHECK-LABEL: masked_mla_nxv4i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mla z0.s, p0/m, z1.s, z2.s
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; CHECK-NEXT: ret
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%mul = mul nsw <vscale x 4 x i32> %b, %c
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%sel = select <vscale x 4 x i1> %mask, <vscale x 4 x i32> %mul, <vscale x 4 x i32> zeroinitializer
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%add = add <vscale x 4 x i32> %a, %sel
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ret <vscale x 4 x i32> %add
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}
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define <vscale x 2 x i64> @masked_mla_nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b, <vscale x 2 x i64> %c, <vscale x 2 x i1> %mask) {
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; CHECK-LABEL: masked_mla_nxv2i64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mla z0.d, p0/m, z1.d, z2.d
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; CHECK-NEXT: ret
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%mul = mul nsw <vscale x 2 x i64> %b, %c
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%sel = select <vscale x 2 x i1> %mask, <vscale x 2 x i64> %mul, <vscale x 2 x i64> zeroinitializer
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%add = add <vscale x 2 x i64> %a, %sel
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ret <vscale x 2 x i64> %add
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}
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;
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; Masked multiply-subtract
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;
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define <vscale x 16 x i8> @masked_mls_nxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c, <vscale x 16 x i1> %mask) {
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; CHECK-LABEL: masked_mls_nxv16i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mls z0.b, p0/m, z1.b, z2.b
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; CHECK-NEXT: ret
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%mul = mul nsw <vscale x 16 x i8> %b, %c
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%sel = select <vscale x 16 x i1> %mask, <vscale x 16 x i8> %mul, <vscale x 16 x i8> zeroinitializer
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%sub = sub <vscale x 16 x i8> %a, %sel
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ret <vscale x 16 x i8> %sub
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}
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define <vscale x 8 x i16> @masked_mls_nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b, <vscale x 8 x i16> %c, <vscale x 8 x i1> %mask) {
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; CHECK-LABEL: masked_mls_nxv8i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mls z0.h, p0/m, z1.h, z2.h
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; CHECK-NEXT: ret
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%mul = mul nsw <vscale x 8 x i16> %b, %c
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%sel = select <vscale x 8 x i1> %mask, <vscale x 8 x i16> %mul, <vscale x 8 x i16> zeroinitializer
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%sub = sub <vscale x 8 x i16> %a, %sel
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ret <vscale x 8 x i16> %sub
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}
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define <vscale x 4 x i32> @masked_mls_nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, <vscale x 4 x i32> %c, <vscale x 4 x i1> %mask) {
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; CHECK-LABEL: masked_mls_nxv4i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mls z0.s, p0/m, z1.s, z2.s
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; CHECK-NEXT: ret
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%mul = mul nsw <vscale x 4 x i32> %b, %c
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%sel = select <vscale x 4 x i1> %mask, <vscale x 4 x i32> %mul, <vscale x 4 x i32> zeroinitializer
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%sub = sub <vscale x 4 x i32> %a, %sel
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ret <vscale x 4 x i32> %sub
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}
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define <vscale x 2 x i64> @masked_mls_nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b, <vscale x 2 x i64> %c, <vscale x 2 x i1> %mask) {
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; CHECK-LABEL: masked_mls_nxv2i64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mls z0.d, p0/m, z1.d, z2.d
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; CHECK-NEXT: ret
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%mul = mul nsw <vscale x 2 x i64> %b, %c
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%sel = select <vscale x 2 x i1> %mask, <vscale x 2 x i64> %mul, <vscale x 2 x i64> zeroinitializer
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%sub = sub <vscale x 2 x i64> %a, %sel
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ret <vscale x 2 x i64> %sub
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}
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