derek.holloway
7502bf64a4
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287 lines
13 KiB
LLVM
287 lines
13 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
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; RUN: llc -mtriple=aarch64--linux-gnu -mattr=+sve < %s | FileCheck %s
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;
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; Masked Loads
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;
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define <vscale x 2 x i64> @masked_zload_nxv2i8(ptr %src, <vscale x 2 x i1> %mask) {
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; CHECK-LABEL: masked_zload_nxv2i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ld1b { z0.d }, p0/z, [x0]
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; CHECK-NEXT: ret
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%load = call <vscale x 2 x i8> @llvm.masked.load.nxv2i8(ptr %src, i32 1, <vscale x 2 x i1> %mask, <vscale x 2 x i8> poison)
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%ext = zext <vscale x 2 x i8> %load to <vscale x 2 x i64>
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ret <vscale x 2 x i64> %ext
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}
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define <vscale x 2 x i64> @masked_zload_nxv2i16(ptr %src, <vscale x 2 x i1> %mask) {
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; CHECK-LABEL: masked_zload_nxv2i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ld1h { z0.d }, p0/z, [x0]
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; CHECK-NEXT: ret
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%load = call <vscale x 2 x i16> @llvm.masked.load.nxv2i16(ptr %src, i32 1, <vscale x 2 x i1> %mask, <vscale x 2 x i16> poison)
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%ext = zext <vscale x 2 x i16> %load to <vscale x 2 x i64>
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ret <vscale x 2 x i64> %ext
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}
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define <vscale x 2 x i64> @masked_zload_nxv2i32(ptr %src, <vscale x 2 x i1> %mask) {
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; CHECK-LABEL: masked_zload_nxv2i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ld1w { z0.d }, p0/z, [x0]
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; CHECK-NEXT: ret
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%load = call <vscale x 2 x i32> @llvm.masked.load.nxv2i32(ptr %src, i32 1, <vscale x 2 x i1> %mask, <vscale x 2 x i32> poison)
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%ext = zext <vscale x 2 x i32> %load to <vscale x 2 x i64>
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ret <vscale x 2 x i64> %ext
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}
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define <vscale x 4 x i32> @masked_zload_nxv4i8(ptr %src, <vscale x 4 x i1> %mask) {
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; CHECK-LABEL: masked_zload_nxv4i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ld1b { z0.s }, p0/z, [x0]
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; CHECK-NEXT: ret
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%load = call <vscale x 4 x i8> @llvm.masked.load.nxv4i8(ptr %src, i32 1, <vscale x 4 x i1> %mask, <vscale x 4 x i8> poison)
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%ext = zext <vscale x 4 x i8> %load to <vscale x 4 x i32>
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ret <vscale x 4 x i32> %ext
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}
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define <vscale x 4 x i32> @masked_zload_nxv4i16(ptr %src, <vscale x 4 x i1> %mask) {
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; CHECK-LABEL: masked_zload_nxv4i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ld1h { z0.s }, p0/z, [x0]
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; CHECK-NEXT: ret
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%load = call <vscale x 4 x i16> @llvm.masked.load.nxv4i16(ptr %src, i32 1, <vscale x 4 x i1> %mask, <vscale x 4 x i16> poison)
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%ext = zext <vscale x 4 x i16> %load to <vscale x 4 x i32>
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ret <vscale x 4 x i32> %ext
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}
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define <vscale x 8 x i16> @masked_zload_nxv8i8(ptr %src, <vscale x 8 x i1> %mask) {
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; CHECK-LABEL: masked_zload_nxv8i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ld1b { z0.h }, p0/z, [x0]
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; CHECK-NEXT: ret
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%load = call <vscale x 8 x i8> @llvm.masked.load.nxv8i8(ptr %src, i32 1, <vscale x 8 x i1> %mask, <vscale x 8 x i8> poison)
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%ext = zext <vscale x 8 x i8> %load to <vscale x 8 x i16>
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ret <vscale x 8 x i16> %ext
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}
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define <vscale x 2 x i64> @masked_zload_passthru(ptr %src, <vscale x 2 x i1> %mask, <vscale x 2 x i32> %passthru) {
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; CHECK-LABEL: masked_zload_passthru:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ld1w { z1.d }, p0/z, [x0]
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; CHECK-NEXT: and z0.d, z0.d, #0xffffffff
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; CHECK-NEXT: mov z0.d, p0/m, z1.d
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; CHECK-NEXT: ret
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%load = call <vscale x 2 x i32> @llvm.masked.load.nxv2i32(ptr %src, i32 1, <vscale x 2 x i1> %mask, <vscale x 2 x i32> %passthru)
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%ext = zext <vscale x 2 x i32> %load to <vscale x 2 x i64>
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ret <vscale x 2 x i64> %ext
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}
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; Return type requires splitting
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define <vscale x 8 x i64> @masked_zload_nxv8i16(ptr %a, <vscale x 8 x i1> %mask) {
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; CHECK-LABEL: masked_zload_nxv8i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ld1h { z0.h }, p0/z, [x0]
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; CHECK-NEXT: uunpklo z1.s, z0.h
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; CHECK-NEXT: uunpkhi z3.s, z0.h
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; CHECK-NEXT: uunpklo z0.d, z1.s
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; CHECK-NEXT: uunpkhi z1.d, z1.s
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; CHECK-NEXT: uunpklo z2.d, z3.s
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; CHECK-NEXT: uunpkhi z3.d, z3.s
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; CHECK-NEXT: ret
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%load = call <vscale x 8 x i16> @llvm.masked.load.nxv8i16(ptr %a, i32 2, <vscale x 8 x i1> %mask, <vscale x 8 x i16> poison)
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%ext = zext <vscale x 8 x i16> %load to <vscale x 8 x i64>
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ret <vscale x 8 x i64> %ext
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}
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; Masked load requires promotion
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define <vscale x 2 x double> @masked_zload_2i16_2f64(ptr noalias %in, <vscale x 2 x i1> %mask) {
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; CHECK-LABEL: masked_zload_2i16_2f64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ld1h { z0.d }, p0/z, [x0]
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; CHECK-NEXT: ptrue p0.d
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; CHECK-NEXT: ucvtf z0.d, p0/m, z0.d
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; CHECK-NEXT: ret
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%wide.load = call <vscale x 2 x i16> @llvm.masked.load.nxv2i16(ptr %in, i32 2, <vscale x 2 x i1> %mask, <vscale x 2 x i16> poison)
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%zext = zext <vscale x 2 x i16> %wide.load to <vscale x 2 x i32>
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%res = uitofp <vscale x 2 x i32> %zext to <vscale x 2 x double>
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ret <vscale x 2 x double> %res
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}
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; Extending loads from unpacked to wide illegal types
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define <vscale x 4 x i64> @masked_zload_4i8_4i64(ptr %a, <vscale x 4 x i1> %b) {
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; CHECK-LABEL: masked_zload_4i8_4i64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ld1b { z1.s }, p0/z, [x0]
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; CHECK-NEXT: uunpklo z0.d, z1.s
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; CHECK-NEXT: uunpkhi z1.d, z1.s
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; CHECK-NEXT: ret
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%aval = call <vscale x 4 x i8> @llvm.masked.load.nxv4i8(ptr %a, i32 16, <vscale x 4 x i1> %b, <vscale x 4 x i8> zeroinitializer)
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%aext = zext <vscale x 4 x i8> %aval to <vscale x 4 x i64>
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ret <vscale x 4 x i64> %aext
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}
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define <vscale x 4 x i64> @masked_zload_4i16_4i64(ptr %a, <vscale x 4 x i1> %b) {
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; CHECK-LABEL: masked_zload_4i16_4i64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ld1h { z1.s }, p0/z, [x0]
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; CHECK-NEXT: uunpklo z0.d, z1.s
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; CHECK-NEXT: uunpkhi z1.d, z1.s
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; CHECK-NEXT: ret
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%aval = call <vscale x 4 x i16> @llvm.masked.load.nxv4i16(ptr %a, i32 16, <vscale x 4 x i1> %b, <vscale x 4 x i16> zeroinitializer)
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%aext = zext <vscale x 4 x i16> %aval to <vscale x 4 x i64>
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ret <vscale x 4 x i64> %aext
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}
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define <vscale x 8 x i32> @masked_zload_8i8_8i32(ptr %a, <vscale x 8 x i1> %b) {
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; CHECK-LABEL: masked_zload_8i8_8i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ld1b { z1.h }, p0/z, [x0]
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; CHECK-NEXT: uunpklo z0.s, z1.h
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; CHECK-NEXT: uunpkhi z1.s, z1.h
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; CHECK-NEXT: ret
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%aval = call <vscale x 8 x i8> @llvm.masked.load.nxv8i8(ptr %a, i32 16, <vscale x 8 x i1> %b, <vscale x 8 x i8> zeroinitializer)
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%aext = zext <vscale x 8 x i8> %aval to <vscale x 8 x i32>
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ret <vscale x 8 x i32> %aext
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}
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define <vscale x 8 x i64> @masked_zload_8i8_8i64(ptr %a, <vscale x 8 x i1> %b) {
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; CHECK-LABEL: masked_zload_8i8_8i64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ld1b { z0.h }, p0/z, [x0]
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; CHECK-NEXT: uunpklo z1.s, z0.h
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; CHECK-NEXT: uunpkhi z3.s, z0.h
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; CHECK-NEXT: uunpklo z0.d, z1.s
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; CHECK-NEXT: uunpkhi z1.d, z1.s
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; CHECK-NEXT: uunpklo z2.d, z3.s
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; CHECK-NEXT: uunpkhi z3.d, z3.s
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; CHECK-NEXT: ret
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%aval = call <vscale x 8 x i8> @llvm.masked.load.nxv8i8(ptr %a, i32 16, <vscale x 8 x i1> %b, <vscale x 8 x i8> zeroinitializer)
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%aext = zext <vscale x 8 x i8> %aval to <vscale x 8 x i64>
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ret <vscale x 8 x i64> %aext
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}
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define <vscale x 4 x i64> @masked_zload_x2_4i8_4i64(ptr %a, ptr %b, <vscale x 4 x i1> %c) {
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; CHECK-LABEL: masked_zload_x2_4i8_4i64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: punpkhi p1.h, p0.b
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; CHECK-NEXT: punpklo p0.h, p0.b
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; CHECK-NEXT: ld1b { z1.d }, p1/z, [x0, #1, mul vl]
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; CHECK-NEXT: ld1b { z2.d }, p1/z, [x1, #1, mul vl]
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; CHECK-NEXT: ld1b { z0.d }, p0/z, [x0]
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; CHECK-NEXT: ld1b { z3.d }, p0/z, [x1]
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; CHECK-NEXT: add z1.d, z1.d, z2.d
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; CHECK-NEXT: add z0.d, z0.d, z3.d
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; CHECK-NEXT: ret
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%aval = call <vscale x 4 x i8> @llvm.masked.load.nxv4i8(ptr %a, i32 16, <vscale x 4 x i1> %c, <vscale x 4 x i8> zeroinitializer)
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%bval = call <vscale x 4 x i8> @llvm.masked.load.nxv4i8(ptr %b, i32 16, <vscale x 4 x i1> %c, <vscale x 4 x i8> zeroinitializer)
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%aext = zext <vscale x 4 x i8> %aval to <vscale x 4 x i64>
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%bext = zext <vscale x 4 x i8> %bval to <vscale x 4 x i64>
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%res = add <vscale x 4 x i64> %aext, %bext
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ret <vscale x 4 x i64> %res
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}
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define <vscale x 4 x i64> @masked_zload_x2_4i16_4i64(ptr %a, ptr %b, <vscale x 4 x i1> %c) {
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; CHECK-LABEL: masked_zload_x2_4i16_4i64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: punpkhi p1.h, p0.b
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; CHECK-NEXT: punpklo p0.h, p0.b
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; CHECK-NEXT: ld1h { z1.d }, p1/z, [x0, #1, mul vl]
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; CHECK-NEXT: ld1h { z2.d }, p1/z, [x1, #1, mul vl]
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; CHECK-NEXT: ld1h { z0.d }, p0/z, [x0]
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; CHECK-NEXT: ld1h { z3.d }, p0/z, [x1]
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; CHECK-NEXT: add z1.d, z1.d, z2.d
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; CHECK-NEXT: add z0.d, z0.d, z3.d
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; CHECK-NEXT: ret
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%aval = call <vscale x 4 x i16> @llvm.masked.load.nxv4i16(ptr %a, i32 16, <vscale x 4 x i1> %c, <vscale x 4 x i16> zeroinitializer)
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%bval = call <vscale x 4 x i16> @llvm.masked.load.nxv4i16(ptr %b, i32 16, <vscale x 4 x i1> %c, <vscale x 4 x i16> zeroinitializer)
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%aext = zext <vscale x 4 x i16> %aval to <vscale x 4 x i64>
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%bext = zext <vscale x 4 x i16> %bval to <vscale x 4 x i64>
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%res = add <vscale x 4 x i64> %aext, %bext
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ret <vscale x 4 x i64> %res
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}
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define <vscale x 8 x i32> @masked_zload_x2_8i8_8i32(ptr %a, ptr %b, <vscale x 8 x i1> %c) {
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; CHECK-LABEL: masked_zload_x2_8i8_8i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: punpkhi p1.h, p0.b
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; CHECK-NEXT: punpklo p0.h, p0.b
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; CHECK-NEXT: ld1b { z1.s }, p1/z, [x0, #1, mul vl]
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; CHECK-NEXT: ld1b { z2.s }, p1/z, [x1, #1, mul vl]
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; CHECK-NEXT: ld1b { z0.s }, p0/z, [x0]
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; CHECK-NEXT: ld1b { z3.s }, p0/z, [x1]
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; CHECK-NEXT: add z1.s, z1.s, z2.s
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; CHECK-NEXT: add z0.s, z0.s, z3.s
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; CHECK-NEXT: ret
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%aval = call <vscale x 8 x i8> @llvm.masked.load.nxv8i8(ptr %a, i32 16, <vscale x 8 x i1> %c, <vscale x 8 x i8> zeroinitializer)
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%bval = call <vscale x 8 x i8> @llvm.masked.load.nxv8i8(ptr %b, i32 16, <vscale x 8 x i1> %c, <vscale x 8 x i8> zeroinitializer)
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%aext = zext <vscale x 8 x i8> %aval to <vscale x 8 x i32>
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%bext = zext <vscale x 8 x i8> %bval to <vscale x 8 x i32>
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%res = add <vscale x 8 x i32> %aext, %bext
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ret <vscale x 8 x i32> %res
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}
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define <vscale x 8 x i64> @masked_zload_x2_8i8_8i64(ptr %a, ptr %b, <vscale x 8 x i1> %c) {
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; CHECK-LABEL: masked_zload_x2_8i8_8i64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: punpkhi p1.h, p0.b
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; CHECK-NEXT: punpklo p0.h, p0.b
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; CHECK-NEXT: punpkhi p2.h, p1.b
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; CHECK-NEXT: punpklo p1.h, p1.b
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; CHECK-NEXT: punpkhi p3.h, p0.b
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; CHECK-NEXT: ld1b { z3.d }, p2/z, [x0, #3, mul vl]
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; CHECK-NEXT: ld1b { z5.d }, p2/z, [x1, #3, mul vl]
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; CHECK-NEXT: punpklo p0.h, p0.b
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; CHECK-NEXT: ld1b { z2.d }, p1/z, [x0, #2, mul vl]
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; CHECK-NEXT: ld1b { z6.d }, p1/z, [x1, #2, mul vl]
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; CHECK-NEXT: ld1b { z1.d }, p3/z, [x0, #1, mul vl]
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; CHECK-NEXT: ld1b { z7.d }, p3/z, [x1, #1, mul vl]
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; CHECK-NEXT: ld1b { z0.d }, p0/z, [x0]
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; CHECK-NEXT: ld1b { z4.d }, p0/z, [x1]
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; CHECK-NEXT: add z3.d, z3.d, z5.d
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; CHECK-NEXT: add z2.d, z2.d, z6.d
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; CHECK-NEXT: add z1.d, z1.d, z7.d
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; CHECK-NEXT: add z0.d, z0.d, z4.d
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; CHECK-NEXT: ret
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%aval = call <vscale x 8 x i8> @llvm.masked.load.nxv8i8(ptr %a, i32 16, <vscale x 8 x i1> %c, <vscale x 8 x i8> zeroinitializer)
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%bval = call <vscale x 8 x i8> @llvm.masked.load.nxv8i8(ptr %b, i32 16, <vscale x 8 x i1> %c, <vscale x 8 x i8> zeroinitializer)
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%aext = zext <vscale x 8 x i8> %aval to <vscale x 8 x i64>
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%bext = zext <vscale x 8 x i8> %bval to <vscale x 8 x i64>
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%res = add <vscale x 8 x i64> %aext, %bext
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ret <vscale x 8 x i64> %res
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}
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define <vscale x 2 x i64> @masked_load_frozen_before_zext(ptr %src, <vscale x 2 x i1> %mask) {
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; CHECK-LABEL: masked_load_frozen_before_zext:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ld1b { z0.d }, p0/z, [x0]
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; CHECK-NEXT: ret
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%load = call <vscale x 2 x i8> @llvm.masked.load.nxv2i8(ptr %src, i32 1, <vscale x 2 x i1> %mask, <vscale x 2 x i8> poison)
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%load.frozen = freeze <vscale x 2 x i8> %load
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%ext = zext <vscale x 2 x i8> %load.frozen to <vscale x 2 x i64>
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ret <vscale x 2 x i64> %ext
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}
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; A multi-use freeze effectively means the load is also multi-use.
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define <vscale x 2 x i64> @masked_load_frozen_before_zext_multiuse(ptr %src, <vscale x 2 x i1> %mask) {
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; CHECK-LABEL: masked_load_frozen_before_zext_multiuse:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ld1b { z0.d }, p0/z, [x0]
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; CHECK-NEXT: // fake_use: $z0
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; CHECK-NEXT: ret
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%load = call <vscale x 2 x i8> @llvm.masked.load.nxv2i8(ptr %src, i32 1, <vscale x 2 x i1> %mask, <vscale x 2 x i8> poison)
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%load.frozen = freeze <vscale x 2 x i8> %load
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%ext = zext <vscale x 2 x i8> %load.frozen to <vscale x 2 x i64>
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call void (...) @llvm.fake.use(<vscale x 2 x i8> %load.frozen)
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ret <vscale x 2 x i64> %ext
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}
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declare <vscale x 2 x i8> @llvm.masked.load.nxv2i8(ptr, i32, <vscale x 2 x i1>, <vscale x 2 x i8>)
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declare <vscale x 2 x i16> @llvm.masked.load.nxv2i16(ptr, i32, <vscale x 2 x i1>, <vscale x 2 x i16>)
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declare <vscale x 2 x i32> @llvm.masked.load.nxv2i32(ptr, i32, <vscale x 2 x i1>, <vscale x 2 x i32>)
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declare <vscale x 4 x i8> @llvm.masked.load.nxv4i8(ptr, i32, <vscale x 4 x i1>, <vscale x 4 x i8>)
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declare <vscale x 4 x i16> @llvm.masked.load.nxv4i16(ptr, i32, <vscale x 4 x i1>, <vscale x 4 x i16>)
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declare <vscale x 8 x i8> @llvm.masked.load.nxv8i8(ptr, i32, <vscale x 8 x i1>, <vscale x 8 x i8>)
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declare <vscale x 8 x i16> @llvm.masked.load.nxv8i16(ptr, i32, <vscale x 8 x i1>, <vscale x 8 x i16>)
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