derek.holloway
7502bf64a4
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219 lines
10 KiB
LLVM
219 lines
10 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s
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; Range checks: for all the instruction tested in this file, the
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; immediate must be within the range [-8, 7] (4-bit immediate). Out of
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; range values are tested only in one case (following). Valid values
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; are tested all through the rest of the file.
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define void @imm_out_of_range(ptr %base, <vscale x 2 x i1> %mask) nounwind {
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; CHECK-LABEL: imm_out_of_range:
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; CHECK: // %bb.0:
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; CHECK-NEXT: rdvl x8, #8
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; CHECK-NEXT: add x8, x0, x8
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; CHECK-NEXT: ldnt1d { z0.d }, p0/z, [x8]
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; CHECK-NEXT: rdvl x8, #-9
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; CHECK-NEXT: add x8, x0, x8
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; CHECK-NEXT: stnt1d { z0.d }, p0, [x8]
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; CHECK-NEXT: ret
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%base_load = getelementptr <vscale x 2 x i64>, ptr %base, i64 8
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%base_load_bc = bitcast ptr %base_load to ptr
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%data = call <vscale x 2 x i64> @llvm.aarch64.sve.ldnt1.nxv2i64(<vscale x 2 x i1> %mask,
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ptr %base_load_bc)
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%base_store = getelementptr <vscale x 2 x i64>, ptr %base, i64 -9
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%base_store_bc = bitcast ptr %base_store to ptr
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call void @llvm.aarch64.sve.stnt1.nxv2i64(<vscale x 2 x i64> %data,
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<vscale x 2 x i1> %mask,
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ptr %base_store_bc)
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ret void
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}
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; 2-lane non-temporal load/stores
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define void @test_masked_ldst_sv2i64(ptr %base, <vscale x 2 x i1> %mask) nounwind {
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; CHECK-LABEL: test_masked_ldst_sv2i64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldnt1d { z0.d }, p0/z, [x0, #-8, mul vl]
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; CHECK-NEXT: stnt1d { z0.d }, p0, [x0, #-7, mul vl]
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; CHECK-NEXT: ret
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%base_load = getelementptr <vscale x 2 x i64>, ptr %base, i64 -8
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%base_load_bc = bitcast ptr %base_load to ptr
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%data = call <vscale x 2 x i64> @llvm.aarch64.sve.ldnt1.nxv2i64(<vscale x 2 x i1> %mask,
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ptr %base_load_bc)
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%base_store = getelementptr <vscale x 2 x i64>, ptr %base, i64 -7
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%base_store_bc = bitcast ptr %base_store to ptr
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call void @llvm.aarch64.sve.stnt1.nxv2i64(<vscale x 2 x i64> %data,
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<vscale x 2 x i1> %mask,
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ptr %base_store_bc)
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ret void
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}
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define void @test_masked_ldst_sv2f64(ptr %base, <vscale x 2 x i1> %mask) nounwind {
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; CHECK-LABEL: test_masked_ldst_sv2f64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldnt1d { z0.d }, p0/z, [x0, #-6, mul vl]
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; CHECK-NEXT: stnt1d { z0.d }, p0, [x0, #-5, mul vl]
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; CHECK-NEXT: ret
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%base_load = getelementptr <vscale x 2 x double>, ptr %base, i64 -6
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%base_load_bc = bitcast ptr %base_load to ptr
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%data = call <vscale x 2 x double> @llvm.aarch64.sve.ldnt1.nxv2f64(<vscale x 2 x i1> %mask,
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ptr %base_load_bc)
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%base_store = getelementptr <vscale x 2 x double>, ptr %base, i64 -5
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%base_store_bc = bitcast ptr %base_store to ptr
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call void @llvm.aarch64.sve.stnt1.nxv2f64(<vscale x 2 x double> %data,
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<vscale x 2 x i1> %mask,
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ptr %base_store_bc)
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ret void
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}
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; 4-lane non-temporal load/stores.
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define void @test_masked_ldst_sv4i32(ptr %base, <vscale x 4 x i1> %mask) nounwind {
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; CHECK-LABEL: test_masked_ldst_sv4i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldnt1w { z0.s }, p0/z, [x0, #6, mul vl]
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; CHECK-NEXT: stnt1w { z0.s }, p0, [x0, #7, mul vl]
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; CHECK-NEXT: ret
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%base_load = getelementptr <vscale x 4 x i32>, ptr %base, i64 6
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%base_load_bc = bitcast ptr %base_load to ptr
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%data = call <vscale x 4 x i32> @llvm.aarch64.sve.ldnt1.nxv4i32(<vscale x 4 x i1> %mask,
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ptr %base_load_bc)
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%base_store = getelementptr <vscale x 4 x i32>, ptr %base, i64 7
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%base_store_bc = bitcast ptr %base_store to ptr
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call void @llvm.aarch64.sve.stnt1.nxv4i32(<vscale x 4 x i32> %data,
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<vscale x 4 x i1> %mask,
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ptr %base_store_bc)
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ret void
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}
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define void @test_masked_ldst_sv4f32(ptr %base, <vscale x 4 x i1> %mask) nounwind {
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; CHECK-LABEL: test_masked_ldst_sv4f32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldnt1w { z0.s }, p0/z, [x0, #-1, mul vl]
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; CHECK-NEXT: stnt1w { z0.s }, p0, [x0, #2, mul vl]
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; CHECK-NEXT: ret
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%base_load = getelementptr <vscale x 4 x float>, ptr %base, i64 -1
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%base_load_bc = bitcast ptr %base_load to ptr
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%data = call <vscale x 4 x float> @llvm.aarch64.sve.ldnt1.nxv4f32(<vscale x 4 x i1> %mask,
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ptr %base_load_bc)
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%base_store = getelementptr <vscale x 4 x float>, ptr %base, i64 2
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%base_store_bc = bitcast ptr %base_store to ptr
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call void @llvm.aarch64.sve.stnt1.nxv4f32(<vscale x 4 x float> %data,
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<vscale x 4 x i1> %mask,
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ptr %base_store_bc)
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ret void
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}
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; 8-lane non-temporal load/stores.
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define void @test_masked_ldst_sv8i16(ptr %base, <vscale x 8 x i1> %mask) nounwind {
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; CHECK-LABEL: test_masked_ldst_sv8i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldnt1h { z0.h }, p0/z, [x0, #6, mul vl]
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; CHECK-NEXT: stnt1h { z0.h }, p0, [x0, #7, mul vl]
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; CHECK-NEXT: ret
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%base_load = getelementptr <vscale x 8 x i16>, ptr %base, i64 6
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%base_load_bc = bitcast ptr %base_load to ptr
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%data = call <vscale x 8 x i16> @llvm.aarch64.sve.ldnt1.nxv8i16(<vscale x 8 x i1> %mask,
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ptr %base_load_bc)
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%base_store = getelementptr <vscale x 8 x i16>, ptr %base, i64 7
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%base_store_bc = bitcast ptr %base_store to ptr
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call void @llvm.aarch64.sve.stnt1.nxv8i16(<vscale x 8 x i16> %data,
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<vscale x 8 x i1> %mask,
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ptr %base_store_bc)
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ret void
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}
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define void @test_masked_ldst_sv8f16(ptr %base, <vscale x 8 x i1> %mask) nounwind {
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; CHECK-LABEL: test_masked_ldst_sv8f16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldnt1h { z0.h }, p0/z, [x0, #-1, mul vl]
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; CHECK-NEXT: stnt1h { z0.h }, p0, [x0, #2, mul vl]
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; CHECK-NEXT: ret
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%base_load = getelementptr <vscale x 8 x half>, ptr %base, i64 -1
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%base_load_bc = bitcast ptr %base_load to ptr
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%data = call <vscale x 8 x half> @llvm.aarch64.sve.ldnt1.nxv8f16(<vscale x 8 x i1> %mask,
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ptr %base_load_bc)
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%base_store = getelementptr <vscale x 8 x half>, ptr %base, i64 2
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%base_store_bc = bitcast ptr %base_store to ptr
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call void @llvm.aarch64.sve.stnt1.nxv8f16(<vscale x 8 x half> %data,
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<vscale x 8 x i1> %mask,
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ptr %base_store_bc)
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ret void
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}
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define void @test_masked_ldst_sv8bf16(ptr %base, <vscale x 8 x i1> %mask) nounwind #0 {
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; CHECK-LABEL: test_masked_ldst_sv8bf16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldnt1h { z0.h }, p0/z, [x0, #-1, mul vl]
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; CHECK-NEXT: stnt1h { z0.h }, p0, [x0, #2, mul vl]
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; CHECK-NEXT: ret
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%base_load = getelementptr <vscale x 8 x bfloat>, ptr %base, i64 -1
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%base_load_bc = bitcast ptr %base_load to ptr
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%data = call <vscale x 8 x bfloat> @llvm.aarch64.sve.ldnt1.nxv8bf16(<vscale x 8 x i1> %mask,
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ptr %base_load_bc)
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%base_store = getelementptr <vscale x 8 x bfloat>, ptr %base, i64 2
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%base_store_bc = bitcast ptr %base_store to ptr
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call void @llvm.aarch64.sve.stnt1.nxv8bf16(<vscale x 8 x bfloat> %data,
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<vscale x 8 x i1> %mask,
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ptr %base_store_bc)
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ret void
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}
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; 16-lane non-temporal load/stores.
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define void @test_masked_ldst_sv16i8(ptr %base, <vscale x 16 x i1> %mask) nounwind {
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; CHECK-LABEL: test_masked_ldst_sv16i8:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldnt1b { z0.b }, p0/z, [x0, #6, mul vl]
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; CHECK-NEXT: stnt1b { z0.b }, p0, [x0, #7, mul vl]
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; CHECK-NEXT: ret
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%base_load = getelementptr <vscale x 16 x i8>, ptr %base, i64 6
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%base_load_bc = bitcast ptr %base_load to ptr
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%data = call <vscale x 16 x i8> @llvm.aarch64.sve.ldnt1.nxv16i8(<vscale x 16 x i1> %mask,
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ptr %base_load_bc)
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%base_store = getelementptr <vscale x 16 x i8>, ptr %base, i64 7
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%base_store_bc = bitcast ptr %base_store to ptr
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call void @llvm.aarch64.sve.stnt1.nxv16i8(<vscale x 16 x i8> %data,
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<vscale x 16 x i1> %mask,
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ptr %base_store_bc)
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ret void
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}
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; 2-element non-temporal loads.
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declare <vscale x 2 x i64> @llvm.aarch64.sve.ldnt1.nxv2i64(<vscale x 2 x i1>, ptr)
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declare <vscale x 2 x double> @llvm.aarch64.sve.ldnt1.nxv2f64(<vscale x 2 x i1>, ptr)
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; 4-element non-temporal loads.
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declare <vscale x 4 x i32> @llvm.aarch64.sve.ldnt1.nxv4i32(<vscale x 4 x i1>, ptr)
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declare <vscale x 4 x float> @llvm.aarch64.sve.ldnt1.nxv4f32(<vscale x 4 x i1>, ptr)
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; 8-element non-temporal loads.
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declare <vscale x 8 x i16> @llvm.aarch64.sve.ldnt1.nxv8i16(<vscale x 8 x i1>, ptr)
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declare <vscale x 8 x half> @llvm.aarch64.sve.ldnt1.nxv8f16(<vscale x 8 x i1>, ptr)
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declare <vscale x 8 x bfloat> @llvm.aarch64.sve.ldnt1.nxv8bf16(<vscale x 8 x i1>, ptr)
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; 16-element non-temporal loads.
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declare <vscale x 16 x i8> @llvm.aarch64.sve.ldnt1.nxv16i8(<vscale x 16 x i1>, ptr)
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; 2-element non-temporal stores.
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declare void @llvm.aarch64.sve.stnt1.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i1>, ptr)
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declare void @llvm.aarch64.sve.stnt1.nxv2f64(<vscale x 2 x double>, <vscale x 2 x i1>, ptr)
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; 4-element non-temporal stores.
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declare void @llvm.aarch64.sve.stnt1.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i1>, ptr)
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declare void @llvm.aarch64.sve.stnt1.nxv4f32(<vscale x 4 x float>, <vscale x 4 x i1>, ptr)
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; 8-element non-temporal stores.
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declare void @llvm.aarch64.sve.stnt1.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i1>, ptr)
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declare void @llvm.aarch64.sve.stnt1.nxv8f16(<vscale x 8 x half>, <vscale x 8 x i1>, ptr)
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declare void @llvm.aarch64.sve.stnt1.nxv8bf16(<vscale x 8 x bfloat>, <vscale x 8 x i1>, ptr)
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; 16-element non-temporal stores.
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declare void @llvm.aarch64.sve.stnt1.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i1>, ptr)
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; +bf16 is required for the bfloat version.
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attributes #0 = { "target-features"="+sve,+bf16" }
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