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TheRock/compiler/amd-llvm/llvm/test/CodeGen/AArch64/sve-ptest-removal-whilelt.mir
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
# RUN: llc -mtriple=aarch64--linux-gnu -mattr=+sve -run-pass=peephole-opt -verify-machineinstrs %s -o - | FileCheck %s
# Test instruction sequences where PTEST is redundant and thus gets removed.
---
name: whilelt_b8_s32
alignment: 2
tracksRegLiveness: true
registers:
- { id: 0, class: gpr32 }
- { id: 1, class: gpr32 }
- { id: 2, class: ppr }
- { id: 3, class: ppr }
- { id: 4, class: gpr32 }
- { id: 5, class: gpr32 }
liveins:
- { reg: '$w0', virtual-reg: '%0' }
- { reg: '$w1', virtual-reg: '%1' }
frameInfo:
maxCallFrameSize: 0
body: |
bb.0.entry:
liveins: $w0, $w1
; CHECK-LABEL: name: whilelt_b8_s32
; CHECK: liveins: $w0, $w1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
; CHECK-NEXT: [[PTRUE_B:%[0-9]+]]:ppr = PTRUE_B 31, implicit $vg
; CHECK-NEXT: [[WHILELT_PWW_B:%[0-9]+]]:ppr = WHILELT_PWW_B [[COPY1]], [[COPY]], implicit-def $nzcv
; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr32 = COPY $wzr
; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr [[COPY2]], $wzr, 0, implicit $nzcv
; CHECK-NEXT: $w0 = COPY [[CSINCWr]]
; CHECK-NEXT: RET_ReallyLR implicit $w0
%1:gpr32 = COPY $w1
%0:gpr32 = COPY $w0
%2:ppr = PTRUE_B 31, implicit $vg
%3:ppr = WHILELT_PWW_B %0, %1, implicit-def dead $nzcv
PTEST_PP killed %2, killed %3, implicit-def $nzcv
%4:gpr32 = COPY $wzr
%5:gpr32 = CSINCWr %4, $wzr, 0, implicit $nzcv
$w0 = COPY %5
RET_ReallyLR implicit $w0
...
---
name: whilelt_b8_s64
alignment: 2
tracksRegLiveness: true
registers:
- { id: 0, class: gpr64 }
- { id: 1, class: gpr64 }
- { id: 2, class: ppr }
- { id: 3, class: ppr }
- { id: 4, class: gpr32 }
- { id: 5, class: gpr32 }
liveins:
- { reg: '$x0', virtual-reg: '%0' }
- { reg: '$x1', virtual-reg: '%1' }
frameInfo:
maxCallFrameSize: 0
body: |
bb.0.entry:
liveins: $x0, $x1
; CHECK-LABEL: name: whilelt_b8_s64
; CHECK: liveins: $x0, $x1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x1
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x0
; CHECK-NEXT: [[PTRUE_B:%[0-9]+]]:ppr = PTRUE_B 31, implicit $vg
; CHECK-NEXT: [[WHILELT_PXX_B:%[0-9]+]]:ppr = WHILELT_PXX_B [[COPY1]], [[COPY]], implicit-def $nzcv
; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr32 = COPY $wzr
; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr [[COPY2]], $wzr, 0, implicit $nzcv
; CHECK-NEXT: $w0 = COPY [[CSINCWr]]
; CHECK-NEXT: RET_ReallyLR implicit $w0
%1:gpr64 = COPY $x1
%0:gpr64 = COPY $x0
%2:ppr = PTRUE_B 31, implicit $vg
%3:ppr = WHILELT_PXX_B %0, %1, implicit-def dead $nzcv
PTEST_PP killed %2, killed %3, implicit-def $nzcv
%4:gpr32 = COPY $wzr
%5:gpr32 = CSINCWr %4, $wzr, 0, implicit $nzcv
$w0 = COPY %5
RET_ReallyLR implicit $w0
...
---
name: whilelt_b16_s32
alignment: 2
tracksRegLiveness: true
registers:
- { id: 0, class: gpr32 }
- { id: 1, class: gpr32 }
- { id: 2, class: ppr }
- { id: 3, class: ppr }
- { id: 4, class: ppr }
- { id: 5, class: ppr }
- { id: 6, class: gpr32 }
- { id: 7, class: gpr32 }
liveins:
- { reg: '$w0', virtual-reg: '%0' }
- { reg: '$w1', virtual-reg: '%1' }
frameInfo:
maxCallFrameSize: 0
body: |
bb.0.entry:
liveins: $w0, $w1
; CHECK-LABEL: name: whilelt_b16_s32
; CHECK: liveins: $w0, $w1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
; CHECK-NEXT: [[PTRUE_H:%[0-9]+]]:ppr = PTRUE_H 31, implicit $vg
; CHECK-NEXT: [[WHILELT_PWW_H:%[0-9]+]]:ppr = WHILELT_PWW_H [[COPY1]], [[COPY]], implicit-def $nzcv
; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr32 = COPY $wzr
; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr [[COPY2]], $wzr, 0, implicit $nzcv
; CHECK-NEXT: $w0 = COPY [[CSINCWr]]
; CHECK-NEXT: RET_ReallyLR implicit $w0
%1:gpr32 = COPY $w1
%0:gpr32 = COPY $w0
%2:ppr = PTRUE_H 31, implicit $vg
%4:ppr = WHILELT_PWW_H %0, %1, implicit-def dead $nzcv
PTEST_PP %2, %4, implicit-def $nzcv
%6:gpr32 = COPY $wzr
%7:gpr32 = CSINCWr %6, $wzr, 0, implicit $nzcv
$w0 = COPY %7
RET_ReallyLR implicit $w0
...
---
name: whilelt_b16_s64
alignment: 2
tracksRegLiveness: true
registers:
- { id: 0, class: gpr64 }
- { id: 1, class: gpr64 }
- { id: 2, class: ppr }
- { id: 3, class: ppr }
- { id: 4, class: ppr }
- { id: 5, class: ppr }
- { id: 6, class: gpr32 }
- { id: 7, class: gpr32 }
liveins:
- { reg: '$x0', virtual-reg: '%0' }
- { reg: '$x1', virtual-reg: '%1' }
frameInfo:
maxCallFrameSize: 0
body: |
bb.0.entry:
liveins: $x0, $x1
; CHECK-LABEL: name: whilelt_b16_s64
; CHECK: liveins: $x0, $x1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x1
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x0
; CHECK-NEXT: [[PTRUE_H:%[0-9]+]]:ppr = PTRUE_H 31, implicit $vg
; CHECK-NEXT: [[WHILELT_PXX_H:%[0-9]+]]:ppr = WHILELT_PXX_H [[COPY1]], [[COPY]], implicit-def $nzcv
; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr32 = COPY $wzr
; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr [[COPY2]], $wzr, 0, implicit $nzcv
; CHECK-NEXT: $w0 = COPY [[CSINCWr]]
; CHECK-NEXT: RET_ReallyLR implicit $w0
%1:gpr64 = COPY $x1
%0:gpr64 = COPY $x0
%2:ppr = PTRUE_H 31, implicit $vg
%4:ppr = WHILELT_PXX_H %0, %1, implicit-def dead $nzcv
PTEST_PP %2, %4, implicit-def $nzcv
%6:gpr32 = COPY $wzr
%7:gpr32 = CSINCWr %6, $wzr, 0, implicit $nzcv
$w0 = COPY %7
RET_ReallyLR implicit $w0
...
---
name: whilelt_b32_s32
alignment: 2
tracksRegLiveness: true
registers:
- { id: 0, class: gpr32 }
- { id: 1, class: gpr32 }
- { id: 2, class: ppr }
- { id: 3, class: ppr }
- { id: 4, class: ppr }
- { id: 5, class: ppr }
- { id: 6, class: gpr32 }
- { id: 7, class: gpr32 }
liveins:
- { reg: '$w0', virtual-reg: '%0' }
- { reg: '$w1', virtual-reg: '%1' }
frameInfo:
maxCallFrameSize: 0
body: |
bb.0.entry:
liveins: $w0, $w1
; CHECK-LABEL: name: whilelt_b32_s32
; CHECK: liveins: $w0, $w1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
; CHECK-NEXT: [[PTRUE_S:%[0-9]+]]:ppr = PTRUE_S 31, implicit $vg
; CHECK-NEXT: [[WHILELT_PWW_S:%[0-9]+]]:ppr = WHILELT_PWW_S [[COPY1]], [[COPY]], implicit-def $nzcv
; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr32 = COPY $wzr
; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr [[COPY2]], $wzr, 0, implicit $nzcv
; CHECK-NEXT: $w0 = COPY [[CSINCWr]]
; CHECK-NEXT: RET_ReallyLR implicit $w0
%1:gpr32 = COPY $w1
%0:gpr32 = COPY $w0
%2:ppr = PTRUE_S 31, implicit $vg
%4:ppr = WHILELT_PWW_S %0, %1, implicit-def dead $nzcv
PTEST_PP %2, %4, implicit-def $nzcv
%6:gpr32 = COPY $wzr
%7:gpr32 = CSINCWr %6, $wzr, 0, implicit $nzcv
$w0 = COPY %7
RET_ReallyLR implicit $w0
...
---
name: whilelt_b32_s64
alignment: 2
tracksRegLiveness: true
registers:
- { id: 0, class: gpr64 }
- { id: 1, class: gpr64 }
- { id: 2, class: ppr }
- { id: 3, class: ppr }
- { id: 4, class: ppr }
- { id: 5, class: ppr }
- { id: 6, class: gpr32 }
- { id: 7, class: gpr32 }
liveins:
- { reg: '$x0', virtual-reg: '%0' }
- { reg: '$x1', virtual-reg: '%1' }
frameInfo:
maxCallFrameSize: 0
body: |
bb.0.entry:
liveins: $x0, $x1
; CHECK-LABEL: name: whilelt_b32_s64
; CHECK: liveins: $x0, $x1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x1
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x0
; CHECK-NEXT: [[PTRUE_S:%[0-9]+]]:ppr = PTRUE_S 31, implicit $vg
; CHECK-NEXT: [[WHILELT_PXX_S:%[0-9]+]]:ppr = WHILELT_PXX_S [[COPY1]], [[COPY]], implicit-def $nzcv
; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr32 = COPY $wzr
; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr [[COPY2]], $wzr, 0, implicit $nzcv
; CHECK-NEXT: $w0 = COPY [[CSINCWr]]
; CHECK-NEXT: RET_ReallyLR implicit $w0
%1:gpr64 = COPY $x1
%0:gpr64 = COPY $x0
%2:ppr = PTRUE_S 31, implicit $vg
%4:ppr = WHILELT_PXX_S %0, %1, implicit-def dead $nzcv
PTEST_PP %2, %4, implicit-def $nzcv
%6:gpr32 = COPY $wzr
%7:gpr32 = CSINCWr %6, $wzr, 0, implicit $nzcv
$w0 = COPY %7
RET_ReallyLR implicit $w0
...
---
name: whilelt_b64_s32
alignment: 2
tracksRegLiveness: true
registers:
- { id: 0, class: gpr32 }
- { id: 1, class: gpr32 }
- { id: 2, class: ppr }
- { id: 3, class: ppr }
- { id: 4, class: ppr }
- { id: 5, class: ppr }
- { id: 6, class: gpr32 }
- { id: 7, class: gpr32 }
liveins:
- { reg: '$w0', virtual-reg: '%0' }
- { reg: '$w1', virtual-reg: '%1' }
frameInfo:
maxCallFrameSize: 0
body: |
bb.0.entry:
liveins: $w0, $w1
; CHECK-LABEL: name: whilelt_b64_s32
; CHECK: liveins: $w0, $w1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
; CHECK-NEXT: [[PTRUE_D:%[0-9]+]]:ppr = PTRUE_D 31, implicit $vg
; CHECK-NEXT: [[WHILELT_PWW_D:%[0-9]+]]:ppr = WHILELT_PWW_D [[COPY1]], [[COPY]], implicit-def $nzcv
; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr32 = COPY $wzr
; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr [[COPY2]], $wzr, 0, implicit $nzcv
; CHECK-NEXT: $w0 = COPY [[CSINCWr]]
; CHECK-NEXT: RET_ReallyLR implicit $w0
%1:gpr32 = COPY $w1
%0:gpr32 = COPY $w0
%2:ppr = PTRUE_D 31, implicit $vg
%4:ppr = WHILELT_PWW_D %0, %1, implicit-def dead $nzcv
PTEST_PP %2, %4, implicit-def $nzcv
%6:gpr32 = COPY $wzr
%7:gpr32 = CSINCWr %6, $wzr, 0, implicit $nzcv
$w0 = COPY %7
RET_ReallyLR implicit $w0
...
---
name: whilelt_b64_s64
alignment: 2
tracksRegLiveness: true
registers:
- { id: 0, class: gpr64 }
- { id: 1, class: gpr64 }
- { id: 2, class: ppr }
- { id: 3, class: ppr }
- { id: 4, class: ppr }
- { id: 5, class: ppr }
- { id: 6, class: gpr32 }
- { id: 7, class: gpr32 }
liveins:
- { reg: '$x0', virtual-reg: '%0' }
- { reg: '$x1', virtual-reg: '%1' }
frameInfo:
maxCallFrameSize: 0
body: |
bb.0.entry:
liveins: $x0, $x1
; CHECK-LABEL: name: whilelt_b64_s64
; CHECK: liveins: $x0, $x1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x1
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x0
; CHECK-NEXT: [[PTRUE_D:%[0-9]+]]:ppr = PTRUE_D 31, implicit $vg
; CHECK-NEXT: [[WHILELT_PXX_D:%[0-9]+]]:ppr = WHILELT_PXX_D [[COPY1]], [[COPY]], implicit-def $nzcv
; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr32 = COPY $wzr
; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr [[COPY2]], $wzr, 0, implicit $nzcv
; CHECK-NEXT: $w0 = COPY [[CSINCWr]]
; CHECK-NEXT: RET_ReallyLR implicit $w0
%1:gpr64 = COPY $x1
%0:gpr64 = COPY $x0
%2:ppr = PTRUE_D 31, implicit $vg
%4:ppr = WHILELT_PXX_D %0, %1, implicit-def dead $nzcv
PTEST_PP %2, %4, implicit-def $nzcv
%6:gpr32 = COPY $wzr
%7:gpr32 = CSINCWr %6, $wzr, 0, implicit $nzcv
$w0 = COPY %7
RET_ReallyLR implicit $w0
...
# PTEST is not redundant when it's Pg operand is not an all active predicate
# of element size matching the WHILELT, which is the implicitly predicate
# used by WHILE when calculating the condition codes.
---
name: whilelt_b64_s32_keep_ptest_not_all_active
alignment: 2
tracksRegLiveness: true
registers:
- { id: 0, class: gpr32 }
- { id: 1, class: gpr32 }
- { id: 2, class: ppr }
- { id: 3, class: ppr }
- { id: 4, class: gpr32 }
- { id: 5, class: gpr32 }
liveins:
- { reg: '$w0', virtual-reg: '%0' }
- { reg: '$w1', virtual-reg: '%1' }
frameInfo:
maxCallFrameSize: 0
body: |
bb.0.entry:
liveins: $w0, $w1
; CHECK-LABEL: name: whilelt_b64_s32_keep_ptest_not_all_active
; CHECK: liveins: $w0, $w1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
; CHECK-NEXT: [[PTRUE_D:%[0-9]+]]:ppr = PTRUE_D 4, implicit $vg
; CHECK-NEXT: [[WHILELT_PWW_D:%[0-9]+]]:ppr = WHILELT_PWW_D [[COPY1]], [[COPY]], implicit-def dead $nzcv
; CHECK-NEXT: PTEST_PP killed [[PTRUE_D]], killed [[WHILELT_PWW_D]], implicit-def $nzcv
; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr32 = COPY $wzr
; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr [[COPY2]], $wzr, 0, implicit $nzcv
; CHECK-NEXT: $w0 = COPY [[CSINCWr]]
; CHECK-NEXT: RET_ReallyLR implicit $w0
%1:gpr32 = COPY $w1
%0:gpr32 = COPY $w0
%2:ppr = PTRUE_D 4, implicit $vg
%3:ppr = WHILELT_PWW_D %0, %1, implicit-def dead $nzcv
PTEST_PP killed %2, killed %3, implicit-def $nzcv
%4:gpr32 = COPY $wzr
%5:gpr32 = CSINCWr %4, $wzr, 0, implicit $nzcv
$w0 = COPY %5
RET_ReallyLR implicit $w0
...
# PTEST is not redundant when it's Pg operand is not an all active predicate
# of element size matching the WHILELT, which is the implicitly predicate
# used by WHILE when calculating the condition codes.
---
name: whilelt_b64_s32_keep_ptest_of_bytes
alignment: 2
tracksRegLiveness: true
registers:
- { id: 0, class: gpr32 }
- { id: 1, class: gpr32 }
- { id: 2, class: ppr }
- { id: 3, class: ppr }
- { id: 4, class: gpr32 }
- { id: 5, class: gpr32 }
liveins:
- { reg: '$w0', virtual-reg: '%0' }
- { reg: '$w1', virtual-reg: '%1' }
frameInfo:
maxCallFrameSize: 0
body: |
bb.0.entry:
liveins: $w0, $w1
; CHECK-LABEL: name: whilelt_b64_s32_keep_ptest_of_bytes
; CHECK: liveins: $w0, $w1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
; CHECK-NEXT: [[PTRUE_B:%[0-9]+]]:ppr = PTRUE_B 31, implicit $vg
; CHECK-NEXT: [[WHILELT_PWW_D:%[0-9]+]]:ppr = WHILELT_PWW_D [[COPY1]], [[COPY]], implicit-def dead $nzcv
; CHECK-NEXT: PTEST_PP killed [[PTRUE_B]], killed [[WHILELT_PWW_D]], implicit-def $nzcv
; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr32 = COPY $wzr
; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr [[COPY2]], $wzr, 0, implicit $nzcv
; CHECK-NEXT: $w0 = COPY [[CSINCWr]]
; CHECK-NEXT: RET_ReallyLR implicit $w0
%1:gpr32 = COPY $w1
%0:gpr32 = COPY $w0
%2:ppr = PTRUE_B 31, implicit $vg
%3:ppr = WHILELT_PWW_D %0, %1, implicit-def dead $nzcv
PTEST_PP killed %2, killed %3, implicit-def $nzcv
%4:gpr32 = COPY $wzr
%5:gpr32 = CSINCWr %4, $wzr, 0, implicit $nzcv
$w0 = COPY %5
RET_ReallyLR implicit $w0
...
# PTEST is not redundant when it's Pg operand is not an all active predicate
# of element size matching the WHILELT, which is the implicitly predicate
# used by WHILE when calculating the condition codes.
---
name: whilelt_b64_s32_keep_ptest_of_halfs
alignment: 2
tracksRegLiveness: true
registers:
- { id: 0, class: gpr32 }
- { id: 1, class: gpr32 }
- { id: 2, class: ppr }
- { id: 3, class: ppr }
- { id: 4, class: gpr32 }
- { id: 5, class: gpr32 }
liveins:
- { reg: '$w0', virtual-reg: '%0' }
- { reg: '$w1', virtual-reg: '%1' }
frameInfo:
maxCallFrameSize: 0
body: |
bb.0.entry:
liveins: $w0, $w1
; CHECK-LABEL: name: whilelt_b64_s32_keep_ptest_of_halfs
; CHECK: liveins: $w0, $w1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
; CHECK-NEXT: [[PTRUE_H:%[0-9]+]]:ppr = PTRUE_H 31, implicit $vg
; CHECK-NEXT: [[WHILELT_PWW_D:%[0-9]+]]:ppr = WHILELT_PWW_D [[COPY1]], [[COPY]], implicit-def dead $nzcv
; CHECK-NEXT: PTEST_PP killed [[PTRUE_H]], killed [[WHILELT_PWW_D]], implicit-def $nzcv
; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr32 = COPY $wzr
; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr [[COPY2]], $wzr, 0, implicit $nzcv
; CHECK-NEXT: $w0 = COPY [[CSINCWr]]
; CHECK-NEXT: RET_ReallyLR implicit $w0
%1:gpr32 = COPY $w1
%0:gpr32 = COPY $w0
%2:ppr = PTRUE_H 31, implicit $vg
%3:ppr = WHILELT_PWW_D %0, %1, implicit-def dead $nzcv
PTEST_PP killed %2, killed %3, implicit-def $nzcv
%4:gpr32 = COPY $wzr
%5:gpr32 = CSINCWr %4, $wzr, 0, implicit $nzcv
$w0 = COPY %5
RET_ReallyLR implicit $w0
...
# PTEST is not redundant when it's Pg operand is not an all active predicate
# of element size matching the WHILELT, which is the implicitly predicate
# used by WHILE when calculating the condition codes.
---
name: whilelt_b64_s32_keep_ptest_of_words
alignment: 2
tracksRegLiveness: true
registers:
- { id: 0, class: gpr32 }
- { id: 1, class: gpr32 }
- { id: 2, class: ppr }
- { id: 3, class: ppr }
- { id: 4, class: gpr32 }
- { id: 5, class: gpr32 }
liveins:
- { reg: '$w0', virtual-reg: '%0' }
- { reg: '$w1', virtual-reg: '%1' }
frameInfo:
maxCallFrameSize: 0
body: |
bb.0.entry:
liveins: $w0, $w1
; CHECK-LABEL: name: whilelt_b64_s32_keep_ptest_of_words
; CHECK: liveins: $w0, $w1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w0
; CHECK-NEXT: [[PTRUE_S:%[0-9]+]]:ppr = PTRUE_S 31, implicit $vg
; CHECK-NEXT: [[WHILELT_PWW_D:%[0-9]+]]:ppr = WHILELT_PWW_D [[COPY1]], [[COPY]], implicit-def dead $nzcv
; CHECK-NEXT: PTEST_PP killed [[PTRUE_S]], killed [[WHILELT_PWW_D]], implicit-def $nzcv
; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr32 = COPY $wzr
; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr [[COPY2]], $wzr, 0, implicit $nzcv
; CHECK-NEXT: $w0 = COPY [[CSINCWr]]
; CHECK-NEXT: RET_ReallyLR implicit $w0
%1:gpr32 = COPY $w1
%0:gpr32 = COPY $w0
%2:ppr = PTRUE_S 31, implicit $vg
%3:ppr = WHILELT_PWW_D %0, %1, implicit-def dead $nzcv
PTEST_PP killed %2, killed %3, implicit-def $nzcv
%4:gpr32 = COPY $wzr
%5:gpr32 = CSINCWr %4, $wzr, 0, implicit $nzcv
$w0 = COPY %5
RET_ReallyLR implicit $w0
...
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