derek.holloway
7502bf64a4
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244 lines
13 KiB
LLVM
244 lines
13 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s | FileCheck %s
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target triple = "aarch64-unknown-linux-gnu"
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define <vscale x 8 x i1> @masked_load_sext_i8i16(ptr %ap, <vscale x 16 x i8> %b) #0 {
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; CHECK-LABEL: masked_load_sext_i8i16:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.b, vl32
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; CHECK-NEXT: cmpeq p1.b, p0/z, z0.b, #0
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; CHECK-NEXT: punpklo p0.h, p1.b
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; CHECK-NEXT: ret
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%p0 = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 10)
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%cmp = call <vscale x 16 x i1> @llvm.aarch64.sve.cmpeq.nxv16i8(<vscale x 16 x i1> %p0, <vscale x 16 x i8> %b, <vscale x 16 x i8> zeroinitializer)
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%extract = call <vscale x 8 x i1> @llvm.vector.extract.nxv8i1.nxv16i1(<vscale x 16 x i1> %cmp, i64 0)
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%ext1 = sext <vscale x 8 x i1> %extract to <vscale x 8 x i16>
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%p1 = call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 10)
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%cmp1 = call <vscale x 8 x i1> @llvm.aarch64.sve.cmpne.nxv8i16(<vscale x 8 x i1> %p1, <vscale x 8 x i16> %ext1, <vscale x 8 x i16> zeroinitializer)
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ret <vscale x 8 x i1> %cmp1
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}
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; This negative test ensures the two ptrues have the same vl
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define <vscale x 8 x i1> @masked_load_sext_i8i16_ptrue_vl(ptr %ap, <vscale x 16 x i8> %b) #0 {
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; CHECK-LABEL: masked_load_sext_i8i16_ptrue_vl:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.b, vl64
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; CHECK-NEXT: cmpeq p1.b, p0/z, z0.b, #0
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; CHECK-NEXT: punpklo p0.h, p1.b
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; CHECK-NEXT: ptrue p1.h, vl32
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; CHECK-NEXT: and p0.b, p0/z, p0.b, p1.b
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; CHECK-NEXT: ret
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%p0 = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 11)
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%cmp = call <vscale x 16 x i1> @llvm.aarch64.sve.cmpeq.nxv16i8(<vscale x 16 x i1> %p0, <vscale x 16 x i8> %b, <vscale x 16 x i8> zeroinitializer)
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%extract = call <vscale x 8 x i1> @llvm.vector.extract.nxv8i1.nxv16i1(<vscale x 16 x i1> %cmp, i64 0)
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%ext1 = sext <vscale x 8 x i1> %extract to <vscale x 8 x i16>
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%p1 = call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 10)
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%cmp1 = call <vscale x 8 x i1> @llvm.aarch64.sve.cmpne.nxv8i16(<vscale x 8 x i1> %p1, <vscale x 8 x i16> %ext1, <vscale x 8 x i16> zeroinitializer)
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ret <vscale x 8 x i1> %cmp1
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}
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; This negative test enforces that both predicates are ptrues
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define <vscale x 8 x i1> @masked_load_sext_i8i16_parg(ptr %ap, <vscale x 16 x i8> %b, <vscale x 16 x i1> %p0) #0 {
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; CHECK-LABEL: masked_load_sext_i8i16_parg:
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; CHECK: // %bb.0:
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; CHECK-NEXT: cmpeq p2.b, p0/z, z0.b, #0
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; CHECK-NEXT: ptrue p1.h, vl32
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; CHECK-NEXT: punpklo p0.h, p2.b
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; CHECK-NEXT: and p0.b, p0/z, p0.b, p1.b
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; CHECK-NEXT: ret
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%cmp = call <vscale x 16 x i1> @llvm.aarch64.sve.cmpeq.nxv16i8(<vscale x 16 x i1> %p0, <vscale x 16 x i8> %b, <vscale x 16 x i8> zeroinitializer)
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%extract = call <vscale x 8 x i1> @llvm.vector.extract.nxv8i1.nxv16i1(<vscale x 16 x i1> %cmp, i64 0)
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%ext1 = sext <vscale x 8 x i1> %extract to <vscale x 8 x i16>
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%p1 = call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 10)
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%cmp1 = call <vscale x 8 x i1> @llvm.aarch64.sve.cmpne.nxv8i16(<vscale x 8 x i1> %p1, <vscale x 8 x i16> %ext1, <vscale x 8 x i16> zeroinitializer)
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ret <vscale x 8 x i1> %cmp1
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}
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define <vscale x 4 x i1> @masked_load_sext_i8i32(ptr %ap, <vscale x 16 x i8> %b) #0 {
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; CHECK-LABEL: masked_load_sext_i8i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.b, vl32
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; CHECK-NEXT: cmpeq p1.b, p0/z, z0.b, #0
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; CHECK-NEXT: punpklo p0.h, p1.b
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; CHECK-NEXT: punpklo p0.h, p0.b
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; CHECK-NEXT: ret
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%p0 = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 10)
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%cmp = call <vscale x 16 x i1> @llvm.aarch64.sve.cmpeq.nxv16i8(<vscale x 16 x i1> %p0, <vscale x 16 x i8> %b, <vscale x 16 x i8> zeroinitializer)
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%extract = call <vscale x 4 x i1> @llvm.vector.extract.nxv4i1.nxv16i1(<vscale x 16 x i1> %cmp, i64 0)
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%ext1 = sext <vscale x 4 x i1> %extract to <vscale x 4 x i32>
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%p1 = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 10)
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%cmp1 = call <vscale x 4 x i1> @llvm.aarch64.sve.cmpne.nxv4i32(<vscale x 4 x i1> %p1, <vscale x 4 x i32> %ext1, <vscale x 4 x i32> zeroinitializer)
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ret <vscale x 4 x i1> %cmp1
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}
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; This negative test ensures the two ptrues have the same vl
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define <vscale x 4 x i1> @masked_load_sext_i8i32_ptrue_vl(ptr %ap, <vscale x 16 x i8> %b) #0 {
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; CHECK-LABEL: masked_load_sext_i8i32_ptrue_vl:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.b, vl64
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; CHECK-NEXT: cmpeq p1.b, p0/z, z0.b, #0
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; CHECK-NEXT: punpklo p0.h, p1.b
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; CHECK-NEXT: ptrue p1.s, vl32
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; CHECK-NEXT: punpklo p0.h, p0.b
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; CHECK-NEXT: and p0.b, p0/z, p0.b, p1.b
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; CHECK-NEXT: ret
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%p0 = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 11)
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%cmp = call <vscale x 16 x i1> @llvm.aarch64.sve.cmpeq.nxv16i8(<vscale x 16 x i1> %p0, <vscale x 16 x i8> %b, <vscale x 16 x i8> zeroinitializer)
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%extract = call <vscale x 4 x i1> @llvm.vector.extract.nxv4i1.nxv16i1(<vscale x 16 x i1> %cmp, i64 0)
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%ext1 = sext <vscale x 4 x i1> %extract to <vscale x 4 x i32>
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%p1 = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 10)
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%cmp1 = call <vscale x 4 x i1> @llvm.aarch64.sve.cmpne.nxv4i32(<vscale x 4 x i1> %p1, <vscale x 4 x i32> %ext1, <vscale x 4 x i32> zeroinitializer)
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ret <vscale x 4 x i1> %cmp1
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}
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; This negative test enforces that both predicates are ptrues
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define <vscale x 4 x i1> @masked_load_sext_i8i32_parg(ptr %ap, <vscale x 16 x i8> %b, <vscale x 16 x i1> %p0) #0 {
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; CHECK-LABEL: masked_load_sext_i8i32_parg:
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; CHECK: // %bb.0:
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; CHECK-NEXT: cmpeq p2.b, p0/z, z0.b, #0
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; CHECK-NEXT: ptrue p1.s, vl32
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; CHECK-NEXT: punpklo p0.h, p2.b
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; CHECK-NEXT: punpklo p0.h, p0.b
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; CHECK-NEXT: and p0.b, p0/z, p0.b, p1.b
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; CHECK-NEXT: ret
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%cmp = call <vscale x 16 x i1> @llvm.aarch64.sve.cmpeq.nxv16i8(<vscale x 16 x i1> %p0, <vscale x 16 x i8> %b, <vscale x 16 x i8> zeroinitializer)
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%extract = call <vscale x 4 x i1> @llvm.vector.extract.nxv4i1.nxv16i1(<vscale x 16 x i1> %cmp, i64 0)
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%ext1 = sext <vscale x 4 x i1> %extract to <vscale x 4 x i32>
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%p1 = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 10)
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%cmp1 = call <vscale x 4 x i1> @llvm.aarch64.sve.cmpne.nxv4i32(<vscale x 4 x i1> %p1, <vscale x 4 x i32> %ext1, <vscale x 4 x i32> zeroinitializer)
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ret <vscale x 4 x i1> %cmp1
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}
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define <vscale x 2 x i1> @masked_load_sext_i8i64(ptr %ap, <vscale x 16 x i8> %b) #0 {
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; CHECK-LABEL: masked_load_sext_i8i64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.b, vl32
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; CHECK-NEXT: cmpeq p1.b, p0/z, z0.b, #0
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; CHECK-NEXT: punpklo p0.h, p1.b
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; CHECK-NEXT: punpklo p0.h, p0.b
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; CHECK-NEXT: punpklo p0.h, p0.b
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; CHECK-NEXT: ret
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%p0 = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 10)
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%cmp = call <vscale x 16 x i1> @llvm.aarch64.sve.cmpeq.nxv16i8(<vscale x 16 x i1> %p0, <vscale x 16 x i8> %b, <vscale x 16 x i8> zeroinitializer)
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%extract = call <vscale x 2 x i1> @llvm.vector.extract.nxv2i1.nxv16i1(<vscale x 16 x i1> %cmp, i64 0)
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%ext1 = sext <vscale x 2 x i1> %extract to <vscale x 2 x i64>
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%p1 = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 10)
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%cmp1 = call <vscale x 2 x i1> @llvm.aarch64.sve.cmpne.nxv2i64(<vscale x 2 x i1> %p1, <vscale x 2 x i64> %ext1, <vscale x 2 x i64> zeroinitializer)
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ret <vscale x 2 x i1> %cmp1
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}
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; This negative test ensures the two ptrues have the same vl
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define <vscale x 2 x i1> @masked_load_sext_i8i64_ptrue_vl(ptr %ap, <vscale x 16 x i8> %b) #0 {
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; CHECK-LABEL: masked_load_sext_i8i64_ptrue_vl:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.b, vl64
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; CHECK-NEXT: cmpeq p1.b, p0/z, z0.b, #0
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; CHECK-NEXT: punpklo p0.h, p1.b
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; CHECK-NEXT: ptrue p1.d, vl32
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; CHECK-NEXT: punpklo p0.h, p0.b
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; CHECK-NEXT: punpklo p0.h, p0.b
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; CHECK-NEXT: and p0.b, p0/z, p0.b, p1.b
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; CHECK-NEXT: ret
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%p0 = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 11)
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%cmp = call <vscale x 16 x i1> @llvm.aarch64.sve.cmpeq.nxv16i8(<vscale x 16 x i1> %p0, <vscale x 16 x i8> %b, <vscale x 16 x i8> zeroinitializer)
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%extract = call <vscale x 2 x i1> @llvm.vector.extract.nxv2i1.nxv16i1(<vscale x 16 x i1> %cmp, i64 0)
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%ext1 = sext <vscale x 2 x i1> %extract to <vscale x 2 x i64>
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%p1 = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 10)
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%cmp1 = call <vscale x 2 x i1> @llvm.aarch64.sve.cmpne.nxv2i64(<vscale x 2 x i1> %p1, <vscale x 2 x i64> %ext1, <vscale x 2 x i64> zeroinitializer)
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ret <vscale x 2 x i1> %cmp1
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}
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; This negative test enforces that both predicates are ptrues
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define <vscale x 2 x i1> @masked_load_sext_i8i64_parg(ptr %ap, <vscale x 16 x i8> %b, <vscale x 16 x i1> %p0) #0 {
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; CHECK-LABEL: masked_load_sext_i8i64_parg:
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; CHECK: // %bb.0:
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; CHECK-NEXT: cmpeq p2.b, p0/z, z0.b, #0
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; CHECK-NEXT: ptrue p1.d, vl32
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; CHECK-NEXT: punpklo p0.h, p2.b
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; CHECK-NEXT: punpklo p0.h, p0.b
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; CHECK-NEXT: punpklo p0.h, p0.b
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; CHECK-NEXT: and p0.b, p0/z, p0.b, p1.b
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; CHECK-NEXT: ret
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%cmp = call <vscale x 16 x i1> @llvm.aarch64.sve.cmpeq.nxv16i8(<vscale x 16 x i1> %p0, <vscale x 16 x i8> %b, <vscale x 16 x i8> zeroinitializer)
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%extract = call <vscale x 2 x i1> @llvm.vector.extract.nxv2i1.nxv16i1(<vscale x 16 x i1> %cmp, i64 0)
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%ext1 = sext <vscale x 2 x i1> %extract to <vscale x 2 x i64>
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%p1 = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 10)
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%cmp1 = call <vscale x 2 x i1> @llvm.aarch64.sve.cmpne.nxv2i64(<vscale x 2 x i1> %p1, <vscale x 2 x i64> %ext1, <vscale x 2 x i64> zeroinitializer)
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ret <vscale x 2 x i1> %cmp1
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}
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; This negative test enforces that the ptrues have a specified vl
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define <vscale x 8 x i1> @masked_load_sext_i8i16_ptrue_all(ptr %ap, <vscale x 16 x i8> %b) #0 {
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; CHECK-LABEL: masked_load_sext_i8i16_ptrue_all:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.b, vl64
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; CHECK-NEXT: cmpeq p1.b, p0/z, z0.b, #0
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; CHECK-NEXT: punpklo p0.h, p1.b
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; CHECK-NEXT: ptrue p1.h, vl32
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; CHECK-NEXT: and p0.b, p0/z, p0.b, p1.b
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; CHECK-NEXT: ret
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%p0 = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 11)
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%cmp = call <vscale x 16 x i1> @llvm.aarch64.sve.cmpeq.nxv16i8(<vscale x 16 x i1> %p0, <vscale x 16 x i8> %b, <vscale x 16 x i8> zeroinitializer)
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%extract = call <vscale x 8 x i1> @llvm.vector.extract.nxv8i1.nxv16i1(<vscale x 16 x i1> %cmp, i64 0)
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%ext1 = sext <vscale x 8 x i1> %extract to <vscale x 8 x i16>
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%p1 = call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 10)
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%cmp1 = call <vscale x 8 x i1> @llvm.aarch64.sve.cmpne.nxv8i16(<vscale x 8 x i1> %p1, <vscale x 8 x i16> %ext1, <vscale x 8 x i16> zeroinitializer)
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ret <vscale x 8 x i1> %cmp1
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}
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; This negative test enforces that the ptrues have a specified vl
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define <vscale x 4 x i1> @masked_load_sext_i8i32_ptrue_all(ptr %ap, <vscale x 16 x i8> %b) #0 {
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; CHECK-LABEL: masked_load_sext_i8i32_ptrue_all:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.b, vl64
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; CHECK-NEXT: cmpeq p1.b, p0/z, z0.b, #0
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; CHECK-NEXT: punpklo p0.h, p1.b
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; CHECK-NEXT: ptrue p1.s, vl32
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; CHECK-NEXT: punpklo p0.h, p0.b
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; CHECK-NEXT: and p0.b, p0/z, p0.b, p1.b
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; CHECK-NEXT: ret
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%p0 = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 11)
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%cmp = call <vscale x 16 x i1> @llvm.aarch64.sve.cmpeq.nxv16i8(<vscale x 16 x i1> %p0, <vscale x 16 x i8> %b, <vscale x 16 x i8> zeroinitializer)
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%extract = call <vscale x 4 x i1> @llvm.vector.extract.nxv4i1.nxv16i1(<vscale x 16 x i1> %cmp, i64 0)
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%ext1 = sext <vscale x 4 x i1> %extract to <vscale x 4 x i32>
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%p1 = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 10)
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%cmp1 = call <vscale x 4 x i1> @llvm.aarch64.sve.cmpne.nxv4i32(<vscale x 4 x i1> %p1, <vscale x 4 x i32> %ext1, <vscale x 4 x i32> zeroinitializer)
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ret <vscale x 4 x i1> %cmp1
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}
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; This negative test enforces that the ptrues have a specified vl
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define <vscale x 2 x i1> @masked_load_sext_i8i64_ptrue_all(ptr %ap, <vscale x 16 x i8> %b) #0 {
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; CHECK-LABEL: masked_load_sext_i8i64_ptrue_all:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ptrue p0.b
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; CHECK-NEXT: cmpeq p1.b, p0/z, z0.b, #0
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; CHECK-NEXT: punpklo p0.h, p1.b
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; CHECK-NEXT: punpklo p0.h, p0.b
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; CHECK-NEXT: punpklo p0.h, p0.b
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; CHECK-NEXT: ret
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%p0 = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 31)
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%cmp = call <vscale x 16 x i1> @llvm.aarch64.sve.cmpeq.nxv16i8(<vscale x 16 x i1> %p0, <vscale x 16 x i8> %b, <vscale x 16 x i8> zeroinitializer)
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%extract = call <vscale x 2 x i1> @llvm.vector.extract.nxv2i1.nxv16i1(<vscale x 16 x i1> %cmp, i64 0)
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%ext1 = sext <vscale x 2 x i1> %extract to <vscale x 2 x i64>
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%p1 = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31)
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%cmp1 = call <vscale x 2 x i1> @llvm.aarch64.sve.cmpne.nxv2i64(<vscale x 2 x i1> %p1, <vscale x 2 x i64> %ext1, <vscale x 2 x i64> zeroinitializer)
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ret <vscale x 2 x i1> %cmp1
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}
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declare <vscale x 16 x i1> @llvm.aarch64.sve.cmpeq.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)
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declare <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32)
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declare <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32)
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declare <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32)
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declare <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32)
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declare <vscale x 8 x i1> @llvm.vector.extract.nxv8i1.nxv16i1(<vscale x 16 x i1>, i64)
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declare <vscale x 4 x i1> @llvm.vector.extract.nxv4i1.nxv16i1(<vscale x 16 x i1>, i64)
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declare <vscale x 2 x i1> @llvm.vector.extract.nxv2i1.nxv16i1(<vscale x 16 x i1>, i64)
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declare <vscale x 8 x i1> @llvm.aarch64.sve.cmpne.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>)
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declare <vscale x 4 x i1> @llvm.aarch64.sve.cmpne.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>)
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declare <vscale x 2 x i1> @llvm.aarch64.sve.cmpne.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>)
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attributes #0 = { "target-features"="+sve" }
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