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Flatten subprojects into a single base monorepo
2026-09-02 16:34:47 -07:00

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -enable-subreg-liveness -mattr=+sve -force-streaming-compatible < %s | FileCheck %s
; RUN: llc -enable-subreg-liveness -mattr=+sme -force-streaming < %s | FileCheck %s
; RUN: llc -enable-subreg-liveness -force-streaming-compatible < %s | FileCheck %s --check-prefix=NONEON-NOSVE
target triple = "aarch64-unknown-linux-gnu"
; i8
define <4 x i8> @vls_sve_and_4xi8(<4 x i8> %b) nounwind {
; CHECK-LABEL: vls_sve_and_4xi8:
; CHECK: // %bb.0:
; CHECK-NEXT: adrp x8, .LCPI0_0
; CHECK-NEXT: ldr d1, [x8, :lo12:.LCPI0_0]
; CHECK-NEXT: and z0.d, z0.d, z1.d
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: vls_sve_and_4xi8:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: str d0, [sp, #-16]!
; NONEON-NOSVE-NEXT: ldrb w8, [sp, #6]
; NONEON-NOSVE-NEXT: strh wzr, [sp, #12]
; NONEON-NOSVE-NEXT: strh wzr, [sp, #8]
; NONEON-NOSVE-NEXT: strh w8, [sp, #14]
; NONEON-NOSVE-NEXT: ldrb w8, [sp, #2]
; NONEON-NOSVE-NEXT: strh w8, [sp, #10]
; NONEON-NOSVE-NEXT: ldr d0, [sp, #8]
; NONEON-NOSVE-NEXT: add sp, sp, #16
; NONEON-NOSVE-NEXT: ret
%c = and <4 x i8> %b, <i8 0, i8 255, i8 0, i8 255>
ret <4 x i8> %c
}
define <8 x i8> @vls_sve_and_8xi8(<8 x i8> %b) nounwind {
; CHECK-LABEL: vls_sve_and_8xi8:
; CHECK: // %bb.0:
; CHECK-NEXT: adrp x8, .LCPI1_0
; CHECK-NEXT: ldr d1, [x8, :lo12:.LCPI1_0]
; CHECK-NEXT: and z0.d, z0.d, z1.d
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: vls_sve_and_8xi8:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: str d0, [sp, #-16]!
; NONEON-NOSVE-NEXT: ldrb w8, [sp, #7]
; NONEON-NOSVE-NEXT: strb wzr, [sp, #14]
; NONEON-NOSVE-NEXT: strb wzr, [sp, #12]
; NONEON-NOSVE-NEXT: strb w8, [sp, #15]
; NONEON-NOSVE-NEXT: ldrb w8, [sp, #5]
; NONEON-NOSVE-NEXT: strb wzr, [sp, #10]
; NONEON-NOSVE-NEXT: strb w8, [sp, #13]
; NONEON-NOSVE-NEXT: ldrb w8, [sp, #3]
; NONEON-NOSVE-NEXT: strb wzr, [sp, #8]
; NONEON-NOSVE-NEXT: strb w8, [sp, #11]
; NONEON-NOSVE-NEXT: ldrb w8, [sp, #1]
; NONEON-NOSVE-NEXT: strb w8, [sp, #9]
; NONEON-NOSVE-NEXT: ldr d0, [sp, #8]
; NONEON-NOSVE-NEXT: add sp, sp, #16
; NONEON-NOSVE-NEXT: ret
%c = and <8 x i8> %b, <i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255>
ret <8 x i8> %c
}
define <16 x i8> @vls_sve_and_16xi8(<16 x i8> %b) nounwind {
; CHECK-LABEL: vls_sve_and_16xi8:
; CHECK: // %bb.0:
; CHECK-NEXT: adrp x8, .LCPI2_0
; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI2_0]
; CHECK-NEXT: and z0.d, z0.d, z1.d
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: vls_sve_and_16xi8:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: str q0, [sp, #-32]!
; NONEON-NOSVE-NEXT: ldrb w8, [sp, #15]
; NONEON-NOSVE-NEXT: strb wzr, [sp, #30]
; NONEON-NOSVE-NEXT: strb wzr, [sp, #28]
; NONEON-NOSVE-NEXT: strb w8, [sp, #31]
; NONEON-NOSVE-NEXT: ldrb w8, [sp, #13]
; NONEON-NOSVE-NEXT: strb wzr, [sp, #26]
; NONEON-NOSVE-NEXT: strb w8, [sp, #29]
; NONEON-NOSVE-NEXT: ldrb w8, [sp, #11]
; NONEON-NOSVE-NEXT: strb wzr, [sp, #24]
; NONEON-NOSVE-NEXT: strb w8, [sp, #27]
; NONEON-NOSVE-NEXT: ldrb w8, [sp, #9]
; NONEON-NOSVE-NEXT: strb wzr, [sp, #22]
; NONEON-NOSVE-NEXT: strb w8, [sp, #25]
; NONEON-NOSVE-NEXT: ldrb w8, [sp, #7]
; NONEON-NOSVE-NEXT: strb wzr, [sp, #20]
; NONEON-NOSVE-NEXT: strb w8, [sp, #23]
; NONEON-NOSVE-NEXT: ldrb w8, [sp, #5]
; NONEON-NOSVE-NEXT: strb wzr, [sp, #18]
; NONEON-NOSVE-NEXT: strb w8, [sp, #21]
; NONEON-NOSVE-NEXT: ldrb w8, [sp, #3]
; NONEON-NOSVE-NEXT: strb wzr, [sp, #16]
; NONEON-NOSVE-NEXT: strb w8, [sp, #19]
; NONEON-NOSVE-NEXT: ldrb w8, [sp, #1]
; NONEON-NOSVE-NEXT: strb w8, [sp, #17]
; NONEON-NOSVE-NEXT: ldr q0, [sp, #16]
; NONEON-NOSVE-NEXT: add sp, sp, #32
; NONEON-NOSVE-NEXT: ret
%c = and <16 x i8> %b, <i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255>
ret <16 x i8> %c
}
define <32 x i8> @vls_sve_and_32xi8(<32 x i8> %ap) nounwind {
; CHECK-LABEL: vls_sve_and_32xi8:
; CHECK: // %bb.0:
; CHECK-NEXT: adrp x8, .LCPI3_0
; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI3_0]
; CHECK-NEXT: and z0.d, z0.d, z2.d
; CHECK-NEXT: and z1.d, z1.d, z2.d
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: vls_sve_and_32xi8:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: stp q0, q1, [sp, #-64]!
; NONEON-NOSVE-NEXT: ldrb w8, [sp, #15]
; NONEON-NOSVE-NEXT: strb wzr, [sp, #46]
; NONEON-NOSVE-NEXT: strb wzr, [sp, #44]
; NONEON-NOSVE-NEXT: strb w8, [sp, #47]
; NONEON-NOSVE-NEXT: ldrb w8, [sp, #13]
; NONEON-NOSVE-NEXT: strb wzr, [sp, #42]
; NONEON-NOSVE-NEXT: strb w8, [sp, #45]
; NONEON-NOSVE-NEXT: ldrb w8, [sp, #11]
; NONEON-NOSVE-NEXT: strb wzr, [sp, #40]
; NONEON-NOSVE-NEXT: strb w8, [sp, #43]
; NONEON-NOSVE-NEXT: ldrb w8, [sp, #9]
; NONEON-NOSVE-NEXT: strb wzr, [sp, #38]
; NONEON-NOSVE-NEXT: strb w8, [sp, #41]
; NONEON-NOSVE-NEXT: ldrb w8, [sp, #7]
; NONEON-NOSVE-NEXT: strb wzr, [sp, #36]
; NONEON-NOSVE-NEXT: strb w8, [sp, #39]
; NONEON-NOSVE-NEXT: ldrb w8, [sp, #5]
; NONEON-NOSVE-NEXT: strb wzr, [sp, #34]
; NONEON-NOSVE-NEXT: strb w8, [sp, #37]
; NONEON-NOSVE-NEXT: ldrb w8, [sp, #3]
; NONEON-NOSVE-NEXT: strb wzr, [sp, #32]
; NONEON-NOSVE-NEXT: strb w8, [sp, #35]
; NONEON-NOSVE-NEXT: ldrb w8, [sp, #1]
; NONEON-NOSVE-NEXT: strb wzr, [sp, #62]
; NONEON-NOSVE-NEXT: strb w8, [sp, #33]
; NONEON-NOSVE-NEXT: ldrb w8, [sp, #31]
; NONEON-NOSVE-NEXT: strb wzr, [sp, #60]
; NONEON-NOSVE-NEXT: strb w8, [sp, #63]
; NONEON-NOSVE-NEXT: ldrb w8, [sp, #29]
; NONEON-NOSVE-NEXT: strb wzr, [sp, #58]
; NONEON-NOSVE-NEXT: strb w8, [sp, #61]
; NONEON-NOSVE-NEXT: ldrb w8, [sp, #27]
; NONEON-NOSVE-NEXT: strb wzr, [sp, #56]
; NONEON-NOSVE-NEXT: strb w8, [sp, #59]
; NONEON-NOSVE-NEXT: ldrb w8, [sp, #25]
; NONEON-NOSVE-NEXT: strb wzr, [sp, #54]
; NONEON-NOSVE-NEXT: strb w8, [sp, #57]
; NONEON-NOSVE-NEXT: ldrb w8, [sp, #23]
; NONEON-NOSVE-NEXT: strb wzr, [sp, #52]
; NONEON-NOSVE-NEXT: strb w8, [sp, #55]
; NONEON-NOSVE-NEXT: ldrb w8, [sp, #21]
; NONEON-NOSVE-NEXT: strb wzr, [sp, #50]
; NONEON-NOSVE-NEXT: strb w8, [sp, #53]
; NONEON-NOSVE-NEXT: ldrb w8, [sp, #19]
; NONEON-NOSVE-NEXT: strb wzr, [sp, #48]
; NONEON-NOSVE-NEXT: strb w8, [sp, #51]
; NONEON-NOSVE-NEXT: ldrb w8, [sp, #17]
; NONEON-NOSVE-NEXT: strb w8, [sp, #49]
; NONEON-NOSVE-NEXT: ldp q0, q1, [sp, #32]
; NONEON-NOSVE-NEXT: add sp, sp, #64
; NONEON-NOSVE-NEXT: ret
%b = and <32 x i8> %ap, <i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255,
i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255>
ret <32 x i8> %b
}
; i16
define <2 x i16> @vls_sve_and_2xi16(<2 x i16> %b) nounwind {
; CHECK-LABEL: vls_sve_and_2xi16:
; CHECK: // %bb.0:
; CHECK-NEXT: fmov s1, wzr
; CHECK-NEXT: mov z0.s, z0.s[1]
; CHECK-NEXT: zip1 z0.s, z1.s, z0.s
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: vls_sve_and_2xi16:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: str d0, [sp, #-16]!
; NONEON-NOSVE-NEXT: ldr w8, [sp, #4]
; NONEON-NOSVE-NEXT: stp wzr, w8, [sp, #8]
; NONEON-NOSVE-NEXT: ldr d0, [sp, #8]
; NONEON-NOSVE-NEXT: add sp, sp, #16
; NONEON-NOSVE-NEXT: ret
%c = and <2 x i16> %b, <i16 0, i16 65535>
ret <2 x i16> %c
}
define <4 x i16> @vls_sve_and_4xi16(<4 x i16> %b) nounwind {
; CHECK-LABEL: vls_sve_and_4xi16:
; CHECK: // %bb.0:
; CHECK-NEXT: adrp x8, .LCPI5_0
; CHECK-NEXT: ldr d1, [x8, :lo12:.LCPI5_0]
; CHECK-NEXT: and z0.d, z0.d, z1.d
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: vls_sve_and_4xi16:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: str d0, [sp, #-16]!
; NONEON-NOSVE-NEXT: ldrh w8, [sp, #6]
; NONEON-NOSVE-NEXT: strh wzr, [sp, #12]
; NONEON-NOSVE-NEXT: strh wzr, [sp, #8]
; NONEON-NOSVE-NEXT: strh w8, [sp, #14]
; NONEON-NOSVE-NEXT: ldrh w8, [sp, #2]
; NONEON-NOSVE-NEXT: strh w8, [sp, #10]
; NONEON-NOSVE-NEXT: ldr d0, [sp, #8]
; NONEON-NOSVE-NEXT: add sp, sp, #16
; NONEON-NOSVE-NEXT: ret
%c = and <4 x i16> %b, <i16 0, i16 65535, i16 0, i16 65535>
ret <4 x i16> %c
}
define <8 x i16> @vls_sve_and_8xi16(<8 x i16> %b) nounwind {
; CHECK-LABEL: vls_sve_and_8xi16:
; CHECK: // %bb.0:
; CHECK-NEXT: adrp x8, .LCPI6_0
; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI6_0]
; CHECK-NEXT: and z0.d, z0.d, z1.d
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: vls_sve_and_8xi16:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: str q0, [sp, #-32]!
; NONEON-NOSVE-NEXT: ldrh w8, [sp, #14]
; NONEON-NOSVE-NEXT: strh wzr, [sp, #28]
; NONEON-NOSVE-NEXT: strh wzr, [sp, #24]
; NONEON-NOSVE-NEXT: strh w8, [sp, #30]
; NONEON-NOSVE-NEXT: ldrh w8, [sp, #10]
; NONEON-NOSVE-NEXT: strh wzr, [sp, #20]
; NONEON-NOSVE-NEXT: strh w8, [sp, #26]
; NONEON-NOSVE-NEXT: ldrh w8, [sp, #6]
; NONEON-NOSVE-NEXT: strh wzr, [sp, #16]
; NONEON-NOSVE-NEXT: strh w8, [sp, #22]
; NONEON-NOSVE-NEXT: ldrh w8, [sp, #2]
; NONEON-NOSVE-NEXT: strh w8, [sp, #18]
; NONEON-NOSVE-NEXT: ldr q0, [sp, #16]
; NONEON-NOSVE-NEXT: add sp, sp, #32
; NONEON-NOSVE-NEXT: ret
%c = and <8 x i16> %b, <i16 0, i16 65535, i16 0, i16 65535, i16 0, i16 65535, i16 0, i16 65535>
ret <8 x i16> %c
}
define <16 x i16> @vls_sve_and_16xi16(<16 x i16> %b) nounwind {
; CHECK-LABEL: vls_sve_and_16xi16:
; CHECK: // %bb.0:
; CHECK-NEXT: adrp x8, .LCPI7_0
; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI7_0]
; CHECK-NEXT: and z0.d, z0.d, z2.d
; CHECK-NEXT: and z1.d, z1.d, z2.d
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: vls_sve_and_16xi16:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: stp q0, q1, [sp, #-64]!
; NONEON-NOSVE-NEXT: ldrh w8, [sp, #14]
; NONEON-NOSVE-NEXT: strh wzr, [sp, #44]
; NONEON-NOSVE-NEXT: strh wzr, [sp, #40]
; NONEON-NOSVE-NEXT: strh w8, [sp, #46]
; NONEON-NOSVE-NEXT: ldrh w8, [sp, #10]
; NONEON-NOSVE-NEXT: strh wzr, [sp, #36]
; NONEON-NOSVE-NEXT: strh w8, [sp, #42]
; NONEON-NOSVE-NEXT: ldrh w8, [sp, #6]
; NONEON-NOSVE-NEXT: strh wzr, [sp, #32]
; NONEON-NOSVE-NEXT: strh w8, [sp, #38]
; NONEON-NOSVE-NEXT: ldrh w8, [sp, #2]
; NONEON-NOSVE-NEXT: strh wzr, [sp, #60]
; NONEON-NOSVE-NEXT: strh w8, [sp, #34]
; NONEON-NOSVE-NEXT: ldrh w8, [sp, #30]
; NONEON-NOSVE-NEXT: strh wzr, [sp, #56]
; NONEON-NOSVE-NEXT: strh w8, [sp, #62]
; NONEON-NOSVE-NEXT: ldrh w8, [sp, #26]
; NONEON-NOSVE-NEXT: strh wzr, [sp, #52]
; NONEON-NOSVE-NEXT: strh w8, [sp, #58]
; NONEON-NOSVE-NEXT: ldrh w8, [sp, #22]
; NONEON-NOSVE-NEXT: strh wzr, [sp, #48]
; NONEON-NOSVE-NEXT: strh w8, [sp, #54]
; NONEON-NOSVE-NEXT: ldrh w8, [sp, #18]
; NONEON-NOSVE-NEXT: strh w8, [sp, #50]
; NONEON-NOSVE-NEXT: ldp q0, q1, [sp, #32]
; NONEON-NOSVE-NEXT: add sp, sp, #64
; NONEON-NOSVE-NEXT: ret
%c = and <16 x i16> %b, <i16 0, i16 65535, i16 0, i16 65535, i16 0, i16 65535, i16 0, i16 65535, i16 0, i16 65535, i16 0, i16 65535, i16 0, i16 65535, i16 0, i16 65535>
ret <16 x i16> %c
}
; i32
define <2 x i32> @vls_sve_and_2xi32(<2 x i32> %b) nounwind {
; CHECK-LABEL: vls_sve_and_2xi32:
; CHECK: // %bb.0:
; CHECK-NEXT: index z1.s, #0, #-1
; CHECK-NEXT: and z0.d, z0.d, z1.d
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: vls_sve_and_2xi32:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: str d0, [sp, #-16]!
; NONEON-NOSVE-NEXT: ldr w8, [sp, #4]
; NONEON-NOSVE-NEXT: stp wzr, w8, [sp, #8]
; NONEON-NOSVE-NEXT: ldr d0, [sp, #8]
; NONEON-NOSVE-NEXT: add sp, sp, #16
; NONEON-NOSVE-NEXT: ret
%c = and <2 x i32> %b, <i32 0, i32 4294967295>
ret <2 x i32> %c
}
define <4 x i32> @vls_sve_and_4xi32(<4 x i32> %b) nounwind {
; CHECK-LABEL: vls_sve_and_4xi32:
; CHECK: // %bb.0:
; CHECK-NEXT: adrp x8, .LCPI9_0
; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI9_0]
; CHECK-NEXT: and z0.d, z0.d, z1.d
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: vls_sve_and_4xi32:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: str q0, [sp, #-32]!
; NONEON-NOSVE-NEXT: ldr w8, [sp, #12]
; NONEON-NOSVE-NEXT: stp wzr, w8, [sp, #24]
; NONEON-NOSVE-NEXT: ldr w8, [sp, #4]
; NONEON-NOSVE-NEXT: stp wzr, w8, [sp, #16]
; NONEON-NOSVE-NEXT: ldr q0, [sp, #16]
; NONEON-NOSVE-NEXT: add sp, sp, #32
; NONEON-NOSVE-NEXT: ret
%c = and <4 x i32> %b, <i32 0, i32 4294967295, i32 0, i32 4294967295>
ret <4 x i32> %c
}
define <8 x i32> @vls_sve_and_8xi32(<8 x i32> %b) nounwind {
; CHECK-LABEL: vls_sve_and_8xi32:
; CHECK: // %bb.0:
; CHECK-NEXT: adrp x8, .LCPI10_0
; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI10_0]
; CHECK-NEXT: and z0.d, z0.d, z2.d
; CHECK-NEXT: and z1.d, z1.d, z2.d
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: vls_sve_and_8xi32:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: stp q0, q1, [sp, #-64]!
; NONEON-NOSVE-NEXT: ldr w8, [sp, #12]
; NONEON-NOSVE-NEXT: stp wzr, w8, [sp, #40]
; NONEON-NOSVE-NEXT: ldr w8, [sp, #4]
; NONEON-NOSVE-NEXT: stp wzr, w8, [sp, #32]
; NONEON-NOSVE-NEXT: ldr w8, [sp, #28]
; NONEON-NOSVE-NEXT: stp wzr, w8, [sp, #56]
; NONEON-NOSVE-NEXT: ldr w8, [sp, #20]
; NONEON-NOSVE-NEXT: stp wzr, w8, [sp, #48]
; NONEON-NOSVE-NEXT: ldp q0, q1, [sp, #32]
; NONEON-NOSVE-NEXT: add sp, sp, #64
; NONEON-NOSVE-NEXT: ret
%c = and <8 x i32> %b, <i32 0, i32 4294967295, i32 0, i32 4294967295, i32 0, i32 4294967295, i32 0, i32 4294967295>
ret <8 x i32> %c
}
; i64
define <2 x i64> @vls_sve_and_2xi64(<2 x i64> %b) nounwind {
; CHECK-LABEL: vls_sve_and_2xi64:
; CHECK: // %bb.0:
; CHECK-NEXT: index z1.d, #0, #-1
; CHECK-NEXT: and z0.d, z0.d, z1.d
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: vls_sve_and_2xi64:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: str q0, [sp, #-32]!
; NONEON-NOSVE-NEXT: ldr x8, [sp, #8]
; NONEON-NOSVE-NEXT: stp xzr, x8, [sp, #16]
; NONEON-NOSVE-NEXT: ldr q0, [sp, #16]
; NONEON-NOSVE-NEXT: add sp, sp, #32
; NONEON-NOSVE-NEXT: ret
%c = and <2 x i64> %b, <i64 0, i64 18446744073709551615>
ret <2 x i64> %c
}
define <4 x i64> @vls_sve_and_4xi64(<4 x i64> %b) nounwind {
; CHECK-LABEL: vls_sve_and_4xi64:
; CHECK: // %bb.0:
; CHECK-NEXT: index z2.d, #0, #-1
; CHECK-NEXT: and z0.d, z0.d, z2.d
; CHECK-NEXT: and z1.d, z1.d, z2.d
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: vls_sve_and_4xi64:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: sub sp, sp, #64
; NONEON-NOSVE-NEXT: str q0, [sp, #32]
; NONEON-NOSVE-NEXT: ldr x8, [sp, #40]
; NONEON-NOSVE-NEXT: str q1, [sp]
; NONEON-NOSVE-NEXT: stp xzr, x8, [sp, #48]
; NONEON-NOSVE-NEXT: ldr x8, [sp, #8]
; NONEON-NOSVE-NEXT: ldr q0, [sp, #48]
; NONEON-NOSVE-NEXT: stp xzr, x8, [sp, #16]
; NONEON-NOSVE-NEXT: ldr q1, [sp, #16]
; NONEON-NOSVE-NEXT: add sp, sp, #64
; NONEON-NOSVE-NEXT: ret
%c = and <4 x i64> %b, <i64 0, i64 18446744073709551615, i64 0, i64 18446744073709551615>
ret <4 x i64> %c
}
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