TheRock/compiler/amd-llvm/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-extract-vector-elt.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -enable-subreg-liveness -mattr=+sve -force-streaming-compatible  < %s | FileCheck %s
; RUN: llc -enable-subreg-liveness -mattr=+sme -force-streaming  < %s | FileCheck %s
; RUN: llc -enable-subreg-liveness -force-streaming-compatible < %s | FileCheck %s --check-prefix=NONEON-NOSVE

target triple = "aarch64-unknown-linux-gnu"

;
; extractelement
;

define half @extractelement_v2f16(<2 x half> %op1) {
; CHECK-LABEL: extractelement_v2f16:
; CHECK:       // %bb.0:
; CHECK-NEXT:    mov z0.h, z0.h[1]
; CHECK-NEXT:    ret
;
; NONEON-NOSVE-LABEL: extractelement_v2f16:
; NONEON-NOSVE:       // %bb.0:
; NONEON-NOSVE-NEXT:    sub sp, sp, #16
; NONEON-NOSVE-NEXT:    .cfi_def_cfa_offset 16
; NONEON-NOSVE-NEXT:    str d0, [sp, #8]
; NONEON-NOSVE-NEXT:    ldr h0, [sp, #10]
; NONEON-NOSVE-NEXT:    add sp, sp, #16
; NONEON-NOSVE-NEXT:    ret
  %r = extractelement <2 x half> %op1, i64 1
  ret half %r
}

define half @extractelement_v4f16(<4 x half> %op1) {
; CHECK-LABEL: extractelement_v4f16:
; CHECK:       // %bb.0:
; CHECK-NEXT:    mov z0.h, z0.h[3]
; CHECK-NEXT:    ret
;
; NONEON-NOSVE-LABEL: extractelement_v4f16:
; NONEON-NOSVE:       // %bb.0:
; NONEON-NOSVE-NEXT:    sub sp, sp, #16
; NONEON-NOSVE-NEXT:    .cfi_def_cfa_offset 16
; NONEON-NOSVE-NEXT:    str d0, [sp, #8]
; NONEON-NOSVE-NEXT:    ldr h0, [sp, #14]
; NONEON-NOSVE-NEXT:    add sp, sp, #16
; NONEON-NOSVE-NEXT:    ret
  %r = extractelement <4 x half> %op1, i64 3
  ret half %r
}

define half @extractelement_v8f16(<8 x half> %op1) {
; CHECK-LABEL: extractelement_v8f16:
; CHECK:       // %bb.0:
; CHECK-NEXT:    mov z0.h, z0.h[7]
; CHECK-NEXT:    ret
;
; NONEON-NOSVE-LABEL: extractelement_v8f16:
; NONEON-NOSVE:       // %bb.0:
; NONEON-NOSVE-NEXT:    str q0, [sp, #-16]!
; NONEON-NOSVE-NEXT:    .cfi_def_cfa_offset 16
; NONEON-NOSVE-NEXT:    ldr h0, [sp, #14]
; NONEON-NOSVE-NEXT:    add sp, sp, #16
; NONEON-NOSVE-NEXT:    ret
  %r = extractelement <8 x half> %op1, i64 7
  ret half %r
}

define half @extractelement_v16f16(ptr %a) {
; CHECK-LABEL: extractelement_v16f16:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ldr q0, [x0, #16]
; CHECK-NEXT:    mov z0.h, z0.h[7]
; CHECK-NEXT:    ret
;
; NONEON-NOSVE-LABEL: extractelement_v16f16:
; NONEON-NOSVE:       // %bb.0:
; NONEON-NOSVE-NEXT:    ldr q0, [x0, #16]
; NONEON-NOSVE-NEXT:    str q0, [sp, #-16]!
; NONEON-NOSVE-NEXT:    .cfi_def_cfa_offset 16
; NONEON-NOSVE-NEXT:    ldr h0, [sp, #14]
; NONEON-NOSVE-NEXT:    add sp, sp, #16
; NONEON-NOSVE-NEXT:    ret
  %op1 = load <16 x half>, ptr %a
  %r = extractelement <16 x half> %op1, i64 15
  ret half %r
}

define float @extractelement_v2f32(<2 x float> %op1) {
; CHECK-LABEL: extractelement_v2f32:
; CHECK:       // %bb.0:
; CHECK-NEXT:    mov z0.s, z0.s[1]
; CHECK-NEXT:    ret
;
; NONEON-NOSVE-LABEL: extractelement_v2f32:
; NONEON-NOSVE:       // %bb.0:
; NONEON-NOSVE-NEXT:    sub sp, sp, #16
; NONEON-NOSVE-NEXT:    .cfi_def_cfa_offset 16
; NONEON-NOSVE-NEXT:    str d0, [sp, #8]
; NONEON-NOSVE-NEXT:    ldr s0, [sp, #12]
; NONEON-NOSVE-NEXT:    add sp, sp, #16
; NONEON-NOSVE-NEXT:    ret
  %r = extractelement <2 x float> %op1, i64 1
  ret float %r
}

define float @extractelement_v4f32(<4 x float> %op1) {
; CHECK-LABEL: extractelement_v4f32:
; CHECK:       // %bb.0:
; CHECK-NEXT:    mov z0.s, z0.s[3]
; CHECK-NEXT:    ret
;
; NONEON-NOSVE-LABEL: extractelement_v4f32:
; NONEON-NOSVE:       // %bb.0:
; NONEON-NOSVE-NEXT:    str q0, [sp, #-16]!
; NONEON-NOSVE-NEXT:    .cfi_def_cfa_offset 16
; NONEON-NOSVE-NEXT:    ldr s0, [sp, #12]
; NONEON-NOSVE-NEXT:    add sp, sp, #16
; NONEON-NOSVE-NEXT:    ret
  %r = extractelement <4 x float> %op1, i64 3
  ret float %r
}

define float @extractelement_v8f32(ptr %a) {
; CHECK-LABEL: extractelement_v8f32:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ldr q0, [x0, #16]
; CHECK-NEXT:    mov z0.s, z0.s[3]
; CHECK-NEXT:    ret
;
; NONEON-NOSVE-LABEL: extractelement_v8f32:
; NONEON-NOSVE:       // %bb.0:
; NONEON-NOSVE-NEXT:    ldr q0, [x0, #16]
; NONEON-NOSVE-NEXT:    str q0, [sp, #-16]!
; NONEON-NOSVE-NEXT:    .cfi_def_cfa_offset 16
; NONEON-NOSVE-NEXT:    ldr s0, [sp, #12]
; NONEON-NOSVE-NEXT:    add sp, sp, #16
; NONEON-NOSVE-NEXT:    ret
  %op1 = load <8 x float>, ptr %a
  %r = extractelement <8 x float> %op1, i64 7
  ret float %r
}

define double @extractelement_v1f64(<1 x double> %op1) {
; CHECK-LABEL: extractelement_v1f64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ret
;
; NONEON-NOSVE-LABEL: extractelement_v1f64:
; NONEON-NOSVE:       // %bb.0:
; NONEON-NOSVE-NEXT:    ret
  %r = extractelement <1 x double> %op1, i64 0
  ret double %r
}
define double @extractelement_v2f64(<2 x double> %op1) {
; CHECK-LABEL: extractelement_v2f64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    mov z0.d, z0.d[1]
; CHECK-NEXT:    ret
;
; NONEON-NOSVE-LABEL: extractelement_v2f64:
; NONEON-NOSVE:       // %bb.0:
; NONEON-NOSVE-NEXT:    str q0, [sp, #-16]!
; NONEON-NOSVE-NEXT:    .cfi_def_cfa_offset 16
; NONEON-NOSVE-NEXT:    ldr d0, [sp, #8]
; NONEON-NOSVE-NEXT:    add sp, sp, #16
; NONEON-NOSVE-NEXT:    ret
  %r = extractelement <2 x double> %op1, i64 1
  ret double %r
}

define double @extractelement_v4f64(ptr %a) {
; CHECK-LABEL: extractelement_v4f64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    ldr q0, [x0, #16]
; CHECK-NEXT:    mov z0.d, z0.d[1]
; CHECK-NEXT:    ret
;
; NONEON-NOSVE-LABEL: extractelement_v4f64:
; NONEON-NOSVE:       // %bb.0:
; NONEON-NOSVE-NEXT:    ldr q0, [x0, #16]
; NONEON-NOSVE-NEXT:    str q0, [sp, #-16]!
; NONEON-NOSVE-NEXT:    .cfi_def_cfa_offset 16
; NONEON-NOSVE-NEXT:    ldr d0, [sp, #8]
; NONEON-NOSVE-NEXT:    add sp, sp, #16
; NONEON-NOSVE-NEXT:    ret
  %op1 = load <4 x double>, ptr %a
  %r = extractelement <4 x double> %op1, i64 3
  ret double %r
}