derek.holloway
7502bf64a4
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176 lines
6.6 KiB
LLVM
176 lines
6.6 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -enable-subreg-liveness -mattr=+sve -force-streaming-compatible < %s | FileCheck %s
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; RUN: llc -enable-subreg-liveness -mattr=+sme -force-streaming < %s | FileCheck %s
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; RUN: llc -enable-subreg-liveness -force-streaming-compatible < %s | FileCheck %s --check-prefix=NONEON-NOSVE
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target triple = "aarch64-unknown-linux-gnu"
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define <2 x i64> @masked_gather_v2i64(ptr %a, ptr %b) vscale_range(2, 2) {
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; CHECK-LABEL: masked_gather_v2i64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: sub sp, sp, #16
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: ptrue p0.d, vl2
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; CHECK-NEXT: ldr q0, [x0]
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; CHECK-NEXT: cmpeq p1.d, p0/z, z0.d, #0
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; CHECK-NEXT: index z0.d, #1, #1
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; CHECK-NEXT: mov z1.d, p1/z, #-1 // =0xffffffffffffffff
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; CHECK-NEXT: and z0.d, z1.d, z0.d
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; CHECK-NEXT: ldr q1, [x1]
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; CHECK-NEXT: uaddv d0, p0, z0.d
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; CHECK-NEXT: ptrue p0.d
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; CHECK-NEXT: str b0, [sp, #12]
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; CHECK-NEXT: ldrb w8, [sp, #12]
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; CHECK-NEXT: tbz w8, #0, .LBB0_2
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; CHECK-NEXT: // %bb.1: // %cond.load
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; CHECK-NEXT: fmov x9, d1
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; CHECK-NEXT: ld1rd { z0.d }, p0/z, [x9]
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; CHECK-NEXT: tbnz w8, #1, .LBB0_3
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; CHECK-NEXT: b .LBB0_4
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; CHECK-NEXT: .LBB0_2:
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; CHECK-NEXT: adrp x9, .LCPI0_0
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; CHECK-NEXT: ldr q0, [x9, :lo12:.LCPI0_0]
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; CHECK-NEXT: tbz w8, #1, .LBB0_4
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; CHECK-NEXT: .LBB0_3: // %cond.load1
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; CHECK-NEXT: mov w8, #1 // =0x1
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; CHECK-NEXT: index z2.d, #0, #1
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; CHECK-NEXT: mov z1.d, z1.d[1]
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; CHECK-NEXT: mov z3.d, x8
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; CHECK-NEXT: fmov x8, d1
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; CHECK-NEXT: cmpeq p1.d, p0/z, z2.d, z3.d
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; CHECK-NEXT: ldr x8, [x8]
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; CHECK-NEXT: mov z0.d, p1/m, x8
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; CHECK-NEXT: .LBB0_4: // %else2
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; CHECK-NEXT: add sp, sp, #16
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; CHECK-NEXT: ret
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;
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; NONEON-NOSVE-LABEL: masked_gather_v2i64:
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; NONEON-NOSVE: // %bb.0:
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; NONEON-NOSVE-NEXT: sub sp, sp, #144
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; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 144
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; NONEON-NOSVE-NEXT: ldr q0, [x0]
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; NONEON-NOSVE-NEXT: ldr q1, [x1]
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; NONEON-NOSVE-NEXT: mov w8, #2 // =0x2
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; NONEON-NOSVE-NEXT: str q0, [sp, #112]
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; NONEON-NOSVE-NEXT: ldp x10, x9, [sp, #112]
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; NONEON-NOSVE-NEXT: cmp x9, #0
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; NONEON-NOSVE-NEXT: csel x8, x8, xzr, eq
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; NONEON-NOSVE-NEXT: cmp x10, #0
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; NONEON-NOSVE-NEXT: csetm x9, eq
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; NONEON-NOSVE-NEXT: sub w8, w8, w9
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; NONEON-NOSVE-NEXT: strb w8, [sp, #140]
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; NONEON-NOSVE-NEXT: and w8, w8, #0xff
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; NONEON-NOSVE-NEXT: tbz w8, #0, .LBB0_2
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; NONEON-NOSVE-NEXT: // %bb.1: // %cond.load
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; NONEON-NOSVE-NEXT: str q1, [sp, #96]
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; NONEON-NOSVE-NEXT: ldr x9, [sp, #96]
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; NONEON-NOSVE-NEXT: ldr x9, [x9]
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; NONEON-NOSVE-NEXT: str x9, [sp, #80]
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; NONEON-NOSVE-NEXT: ldr q0, [sp, #80]
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; NONEON-NOSVE-NEXT: tbnz w8, #1, .LBB0_3
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; NONEON-NOSVE-NEXT: b .LBB0_4
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; NONEON-NOSVE-NEXT: .LBB0_2:
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; NONEON-NOSVE-NEXT: adrp x9, .LCPI0_0
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; NONEON-NOSVE-NEXT: ldr q0, [x9, :lo12:.LCPI0_0]
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; NONEON-NOSVE-NEXT: tbz w8, #1, .LBB0_4
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; NONEON-NOSVE-NEXT: .LBB0_3: // %cond.load1
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; NONEON-NOSVE-NEXT: str q1, [sp, #64]
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; NONEON-NOSVE-NEXT: ldr x8, [sp, #72]
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; NONEON-NOSVE-NEXT: ldr x8, [x8]
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; NONEON-NOSVE-NEXT: str q0, [sp]
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; NONEON-NOSVE-NEXT: ldr x9, [sp]
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; NONEON-NOSVE-NEXT: str x8, [sp, #48]
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; NONEON-NOSVE-NEXT: ldr q0, [sp, #48]
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; NONEON-NOSVE-NEXT: str q0, [sp, #16]
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; NONEON-NOSVE-NEXT: ldr x8, [sp, #16]
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; NONEON-NOSVE-NEXT: stp x9, x8, [sp, #32]
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; NONEON-NOSVE-NEXT: ldr q0, [sp, #32]
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; NONEON-NOSVE-NEXT: .LBB0_4: // %else2
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; NONEON-NOSVE-NEXT: add sp, sp, #144
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; NONEON-NOSVE-NEXT: ret
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%vals = load <2 x i64>, ptr %a
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%ptrs = load <2 x ptr>, ptr %b
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%mask = icmp eq <2 x i64> %vals, zeroinitializer
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%res = call <2 x i64> @llvm.masked.gather.v2i64(<2 x ptr> %ptrs, i32 8, <2 x i1> %mask, <2 x i64> poison)
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ret <2 x i64> %res
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}
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define void @masked_scatter_v2i64(ptr %a, ptr %b) vscale_range(2, 2) {
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; CHECK-LABEL: masked_scatter_v2i64:
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; CHECK: // %bb.0:
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; CHECK-NEXT: sub sp, sp, #16
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: ptrue p0.d, vl2
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; CHECK-NEXT: ldr q0, [x0]
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; CHECK-NEXT: index z1.d, #1, #1
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; CHECK-NEXT: cmpeq p1.d, p0/z, z0.d, #0
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; CHECK-NEXT: mov z2.d, p1/z, #-1 // =0xffffffffffffffff
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; CHECK-NEXT: and z1.d, z2.d, z1.d
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; CHECK-NEXT: uaddv d2, p0, z1.d
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; CHECK-NEXT: ldr q1, [x1]
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; CHECK-NEXT: str b2, [sp, #12]
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; CHECK-NEXT: ldrb w8, [sp, #12]
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; CHECK-NEXT: tbnz w8, #0, .LBB1_3
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; CHECK-NEXT: // %bb.1: // %else
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; CHECK-NEXT: tbnz w8, #1, .LBB1_4
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; CHECK-NEXT: .LBB1_2: // %else2
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; CHECK-NEXT: add sp, sp, #16
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; CHECK-NEXT: ret
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; CHECK-NEXT: .LBB1_3: // %cond.store
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; CHECK-NEXT: fmov x9, d1
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; CHECK-NEXT: str d0, [x9]
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; CHECK-NEXT: tbz w8, #1, .LBB1_2
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; CHECK-NEXT: .LBB1_4: // %cond.store1
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; CHECK-NEXT: mov z1.d, z1.d[1]
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; CHECK-NEXT: mov z0.d, z0.d[1]
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; CHECK-NEXT: fmov x8, d1
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; CHECK-NEXT: str d0, [x8]
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; CHECK-NEXT: add sp, sp, #16
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; CHECK-NEXT: ret
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;
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; NONEON-NOSVE-LABEL: masked_scatter_v2i64:
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; NONEON-NOSVE: // %bb.0:
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; NONEON-NOSVE-NEXT: sub sp, sp, #96
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; NONEON-NOSVE-NEXT: .cfi_def_cfa_offset 96
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; NONEON-NOSVE-NEXT: ldr q1, [x0]
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; NONEON-NOSVE-NEXT: ldr q0, [x1]
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; NONEON-NOSVE-NEXT: mov w8, #2 // =0x2
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; NONEON-NOSVE-NEXT: str q1, [sp, #64]
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; NONEON-NOSVE-NEXT: ldp x10, x9, [sp, #64]
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; NONEON-NOSVE-NEXT: cmp x9, #0
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; NONEON-NOSVE-NEXT: csel x8, x8, xzr, eq
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; NONEON-NOSVE-NEXT: cmp x10, #0
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; NONEON-NOSVE-NEXT: csetm x9, eq
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; NONEON-NOSVE-NEXT: sub w8, w8, w9
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; NONEON-NOSVE-NEXT: strb w8, [sp, #92]
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; NONEON-NOSVE-NEXT: and w8, w8, #0xff
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; NONEON-NOSVE-NEXT: tbnz w8, #0, .LBB1_3
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; NONEON-NOSVE-NEXT: // %bb.1: // %else
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; NONEON-NOSVE-NEXT: tbnz w8, #1, .LBB1_4
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; NONEON-NOSVE-NEXT: .LBB1_2: // %else2
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; NONEON-NOSVE-NEXT: add sp, sp, #96
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; NONEON-NOSVE-NEXT: ret
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; NONEON-NOSVE-NEXT: .LBB1_3: // %cond.store
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; NONEON-NOSVE-NEXT: stp q1, q0, [sp, #32]
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; NONEON-NOSVE-NEXT: ldr x9, [sp, #32]
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; NONEON-NOSVE-NEXT: ldr x10, [sp, #48]
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; NONEON-NOSVE-NEXT: str x9, [x10]
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; NONEON-NOSVE-NEXT: tbz w8, #1, .LBB1_2
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; NONEON-NOSVE-NEXT: .LBB1_4: // %cond.store1
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; NONEON-NOSVE-NEXT: stp q1, q0, [sp]
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; NONEON-NOSVE-NEXT: ldr x8, [sp, #8]
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; NONEON-NOSVE-NEXT: ldr x9, [sp, #24]
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; NONEON-NOSVE-NEXT: str x8, [x9]
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; NONEON-NOSVE-NEXT: add sp, sp, #96
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; NONEON-NOSVE-NEXT: ret
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%vals = load <2 x i64>, ptr %a
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%ptrs = load <2 x ptr>, ptr %b
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%mask = icmp eq <2 x i64> %vals, zeroinitializer
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call void @llvm.masked.scatter.v2i64(<2 x i64> %vals, <2 x ptr> %ptrs, i32 8, <2 x i1> %mask)
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ret void
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}
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declare void @llvm.masked.scatter.v2i64(<2 x i64>, <2 x ptr>, i32, <2 x i1>)
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declare <2 x i64> @llvm.masked.gather.v2i64(<2 x ptr>, i32, <2 x i1>, <2 x i64>)
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