derek.holloway
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103 lines
4.5 KiB
LLVM
103 lines
4.5 KiB
LLVM
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2 < %s | FileCheck %s
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;
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; ADCLB (vector, long, unpredicated)
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;
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define <vscale x 4 x i32> @adclb_i32(<vscale x 4 x i32> %a,
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<vscale x 4 x i32> %b,
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<vscale x 4 x i32> %c) {
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; CHECK-LABEL: adclb_i32
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; CHECK: adclb z0.s, z1.s, z2.s
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; CHECK-NEXT: ret
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%res = call <vscale x 4 x i32> @llvm.aarch64.sve.adclb.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, <vscale x 4 x i32> %c)
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ret <vscale x 4 x i32> %res
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}
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define <vscale x 2 x i64> @adclb_i64(<vscale x 2 x i64> %a,
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<vscale x 2 x i64> %b,
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<vscale x 2 x i64> %c) {
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; CHECK-LABEL: adclb_i64
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; CHECK: adclb z0.d, z1.d, z2.d
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; CHECK-NEXT: ret
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%res = call <vscale x 2 x i64> @llvm.aarch64.sve.adclb.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b, <vscale x 2 x i64> %c)
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ret <vscale x 2 x i64> %res
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}
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;
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; ADCLT (vector, long, unpredicated)
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;
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define <vscale x 4 x i32> @adclt_i32(<vscale x 4 x i32> %a,
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<vscale x 4 x i32> %b,
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<vscale x 4 x i32> %c) {
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; CHECK-LABEL: adclt_i32
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; CHECK: adclt z0.s, z1.s, z2.s
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; CHECK-NEXT: ret
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%res = call <vscale x 4 x i32> @llvm.aarch64.sve.adclt.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, <vscale x 4 x i32> %c)
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ret <vscale x 4 x i32> %res
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}
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define <vscale x 2 x i64> @adclt_i64(<vscale x 2 x i64> %a,
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<vscale x 2 x i64> %b,
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<vscale x 2 x i64> %c) {
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; CHECK-LABEL: adclt_i64
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; CHECK: adclt z0.d, z1.d, z2.d
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; CHECK-NEXT: ret
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%res = call <vscale x 2 x i64> @llvm.aarch64.sve.adclt.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b, <vscale x 2 x i64> %c)
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ret <vscale x 2 x i64> %res
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}
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;
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; SBCLB (vector, long, unpredicated)
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;
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define <vscale x 4 x i32> @sbclb_i32(<vscale x 4 x i32> %a,
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<vscale x 4 x i32> %b,
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<vscale x 4 x i32> %c) {
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; CHECK-LABEL: sbclb_i32
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; CHECK: sbclb z0.s, z1.s, z2.s
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; CHECK-NEXT: ret
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%res = call <vscale x 4 x i32> @llvm.aarch64.sve.sbclb.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, <vscale x 4 x i32> %c)
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ret <vscale x 4 x i32> %res
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}
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define <vscale x 2 x i64> @sbclb_i64(<vscale x 2 x i64> %a,
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<vscale x 2 x i64> %b,
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<vscale x 2 x i64> %c) {
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; CHECK-LABEL: sbclb_i64
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; CHECK: sbclb z0.d, z1.d, z2.d
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; CHECK-NEXT: ret
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%res = call <vscale x 2 x i64> @llvm.aarch64.sve.sbclb.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b, <vscale x 2 x i64> %c)
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ret <vscale x 2 x i64> %res
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}
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;
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; SBCLT (vector, long, unpredicated)
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;
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define <vscale x 4 x i32> @sbclt_i32(<vscale x 4 x i32> %a,
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<vscale x 4 x i32> %b,
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<vscale x 4 x i32> %c) {
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; CHECK-LABEL: sbclt_i32
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; CHECK: sbclt z0.s, z1.s, z2.s
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; CHECK-NEXT: ret
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%res = call <vscale x 4 x i32> @llvm.aarch64.sve.sbclt.nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b, <vscale x 4 x i32> %c)
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ret <vscale x 4 x i32> %res
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}
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define <vscale x 2 x i64> @sbclt_i64(<vscale x 2 x i64> %a,
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<vscale x 2 x i64> %b,
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<vscale x 2 x i64> %c) {
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; CHECK-LABEL: sbclt_i64
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; CHECK: sbclt z0.d, z1.d, z2.d
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; CHECK-NEXT: ret
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%res = call <vscale x 2 x i64> @llvm.aarch64.sve.sbclt.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b, <vscale x 2 x i64> %c)
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ret <vscale x 2 x i64> %res
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}
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declare <vscale x 4 x i32> @llvm.aarch64.sve.adclb.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>)
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declare <vscale x 2 x i64> @llvm.aarch64.sve.adclb.nxv2i64(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>)
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declare <vscale x 4 x i32> @llvm.aarch64.sve.adclt.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>)
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declare <vscale x 2 x i64> @llvm.aarch64.sve.adclt.nxv2i64(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>)
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declare <vscale x 4 x i32> @llvm.aarch64.sve.sbclb.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>)
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declare <vscale x 2 x i64> @llvm.aarch64.sve.sbclb.nxv2i64(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>)
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declare <vscale x 4 x i32> @llvm.aarch64.sve.sbclt.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>)
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declare <vscale x 2 x i64> @llvm.aarch64.sve.sbclt.nxv2i64(<vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>)
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