derek.holloway
7502bf64a4
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161 lines
6.2 KiB
LLVM
161 lines
6.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2p1,+bf16 < %s | FileCheck %s --check-prefixes=CHECK,SVE
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; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme2p1,+bf16 -force-streaming < %s | FileCheck %s --check-prefixes=CHECK,SME
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define void @dupq_i8_256b(ptr %addr) #0 {
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; CHECK-LABEL: dupq_i8_256b:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldr z0, [x0]
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; CHECK-NEXT: dupq z0.b, z0.b[15]
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; CHECK-NEXT: str z0, [x0]
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; CHECK-NEXT: ret
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%load = load <32 x i8>, ptr %addr
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%splat.lanes = shufflevector <32 x i8> %load, <32 x i8> poison, <32 x i32> <i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15,
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i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31>
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store <32 x i8> %splat.lanes, ptr %addr
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ret void
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}
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define void @dupq_i16_256b(ptr %addr) #0 {
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; CHECK-LABEL: dupq_i16_256b:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldr z0, [x0]
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; CHECK-NEXT: dupq z0.h, z0.h[2]
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; CHECK-NEXT: str z0, [x0]
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; CHECK-NEXT: ret
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%load = load <16 x i16>, ptr %addr
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%splat.lanes = shufflevector <16 x i16> %load, <16 x i16> poison, <16 x i32> <i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2,
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i32 10, i32 10, i32 10, i32 10, i32 10, i32 10, i32 10, i32 10>
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store <16 x i16> %splat.lanes, ptr %addr
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ret void
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}
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define void @dupq_i32_256b(ptr %addr) #0 {
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; CHECK-LABEL: dupq_i32_256b:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldr z0, [x0]
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; CHECK-NEXT: dupq z0.s, z0.s[3]
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; CHECK-NEXT: str z0, [x0]
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; CHECK-NEXT: ret
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%load = load <8 x i32>, ptr %addr
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%splat.lanes = shufflevector <8 x i32> %load, <8 x i32> poison, <8 x i32> <i32 3, i32 3, i32 3, i32 3,
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i32 7, i32 7, i32 7, i32 7>
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store <8 x i32> %splat.lanes, ptr %addr
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ret void
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}
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define void @dupq_i64_256b(ptr %addr) #0 {
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; CHECK-LABEL: dupq_i64_256b:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldr z0, [x0]
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; CHECK-NEXT: trn1 z0.d, z0.d, z0.d
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; CHECK-NEXT: str z0, [x0]
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; CHECK-NEXT: ret
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%load = load <4 x i64>, ptr %addr
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%splat.lanes = shufflevector <4 x i64> %load, <4 x i64> poison, <4 x i32> <i32 0, i32 0, i32 2, i32 2>
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store <4 x i64> %splat.lanes, ptr %addr
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ret void
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}
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define void @dupq_f16_256b(ptr %addr) #0 {
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; CHECK-LABEL: dupq_f16_256b:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldr z0, [x0]
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; CHECK-NEXT: dupq z0.h, z0.h[2]
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; CHECK-NEXT: str z0, [x0]
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; CHECK-NEXT: ret
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%load = load <16 x half>, ptr %addr
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%splat.lanes = shufflevector <16 x half> %load, <16 x half> poison, <16 x i32> <i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2,
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i32 10, i32 10, i32 10, i32 10, i32 10, i32 10, i32 10, i32 10>
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store <16 x half> %splat.lanes, ptr %addr
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ret void
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}
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define void @dupq_bf16_256b(ptr %addr) #0 {
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; SVE-LABEL: dupq_bf16_256b:
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; SVE: // %bb.0:
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; SVE-NEXT: ldp q0, q1, [x0]
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; SVE-NEXT: dup v0.8h, v0.h[2]
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; SVE-NEXT: dup v1.8h, v1.h[2]
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; SVE-NEXT: stp q0, q1, [x0]
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; SVE-NEXT: ret
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;
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; SME-LABEL: dupq_bf16_256b:
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; SME: // %bb.0:
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; SME-NEXT: ldp q1, q0, [x0]
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; SME-NEXT: str q0, [sp, #-64]!
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; SME-NEXT: .cfi_def_cfa_offset 64
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; SME-NEXT: ldr h0, [sp, #4]
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; SME-NEXT: str q1, [sp, #32]
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; SME-NEXT: str h0, [sp, #30]
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; SME-NEXT: str h0, [sp, #28]
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; SME-NEXT: str h0, [sp, #26]
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; SME-NEXT: str h0, [sp, #24]
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; SME-NEXT: str h0, [sp, #22]
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; SME-NEXT: str h0, [sp, #20]
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; SME-NEXT: str h0, [sp, #18]
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; SME-NEXT: str h0, [sp, #16]
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; SME-NEXT: ldr h0, [sp, #36]
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; SME-NEXT: ldr q1, [sp, #16]
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; SME-NEXT: str h0, [sp, #62]
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; SME-NEXT: str h0, [sp, #60]
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; SME-NEXT: str h0, [sp, #58]
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; SME-NEXT: str h0, [sp, #56]
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; SME-NEXT: str h0, [sp, #54]
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; SME-NEXT: str h0, [sp, #52]
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; SME-NEXT: str h0, [sp, #50]
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; SME-NEXT: str h0, [sp, #48]
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; SME-NEXT: ldr q0, [sp, #48]
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; SME-NEXT: stp q0, q1, [x0]
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; SME-NEXT: add sp, sp, #64
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; SME-NEXT: ret
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%load = load <16 x bfloat>, ptr %addr
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%splat.lanes = shufflevector <16 x bfloat> %load, <16 x bfloat> poison, <16 x i32> <i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2,
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i32 10, i32 10, i32 10, i32 10, i32 10, i32 10, i32 10, i32 10>
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store <16 x bfloat> %splat.lanes, ptr %addr
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ret void
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}
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define void @dupq_f32_256b(ptr %addr) #0 {
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; CHECK-LABEL: dupq_f32_256b:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldr z0, [x0]
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; CHECK-NEXT: dupq z0.s, z0.s[3]
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; CHECK-NEXT: str z0, [x0]
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; CHECK-NEXT: ret
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%load = load <8 x float>, ptr %addr
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%splat.lanes = shufflevector <8 x float> %load, <8 x float> poison, <8 x i32> <i32 3, i32 3, i32 3, i32 3,
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i32 7, i32 7, i32 7, i32 7>
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store <8 x float> %splat.lanes, ptr %addr
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ret void
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}
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define void @dupq_f64_256b(ptr %addr) #0 {
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; CHECK-LABEL: dupq_f64_256b:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldr z0, [x0]
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; CHECK-NEXT: trn1 z0.d, z0.d, z0.d
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; CHECK-NEXT: str z0, [x0]
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; CHECK-NEXT: ret
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%load = load <4 x double>, ptr %addr
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%splat.lanes = shufflevector <4 x double> %load, <4 x double> poison, <4 x i32> <i32 0, i32 0, i32 2, i32 2>
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store <4 x double> %splat.lanes, ptr %addr
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ret void
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}
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define void @dupq_f32_256b_with_poison(ptr %addr) #0 {
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; CHECK-LABEL: dupq_f32_256b_with_poison:
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; CHECK: // %bb.0:
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; CHECK-NEXT: ldr z0, [x0]
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; CHECK-NEXT: dupq z0.s, z0.s[3]
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; CHECK-NEXT: str z0, [x0]
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; CHECK-NEXT: ret
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%load = load <8 x float>, ptr %addr
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%splat.lanes = shufflevector <8 x float> %load, <8 x float> poison, <8 x i32> <i32 3, i32 poison, i32 3, i32 3,
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i32 7, i32 7, i32 7, i32 poison>
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store <8 x float> %splat.lanes, ptr %addr
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ret void
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}
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attributes #0 = { noinline vscale_range(2,2) }
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