derek.holloway
7502bf64a4
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155 lines
4.7 KiB
LLVM
155 lines
4.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=aarch64 -mattr=+sve2 | FileCheck %s -check-prefixes=CHECK-SVE2
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; RUN: llc < %s -mtriple=aarch64 -mattr=+sve | FileCheck %s -check-prefixes=CHECK-SVE
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; RUN: llc < %s -mtriple=aarch64 | FileCheck %s -check-prefixes=CHECK
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define i64 @smax(<2 x i64> %0) {
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; CHECK-SVE2-LABEL: smax:
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; CHECK-SVE2: // %bb.0:
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; CHECK-SVE2-NEXT: ptrue p0.d, vl2
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; CHECK-SVE2-NEXT: // kill: def $q0 killed $q0 def $z0
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; CHECK-SVE2-NEXT: smaxp z0.d, p0/m, z0.d, z0.d
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; CHECK-SVE2-NEXT: fmov x0, d0
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; CHECK-SVE2-NEXT: ret
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;
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; CHECK-SVE-LABEL: smax:
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; CHECK-SVE: // %bb.0:
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; CHECK-SVE-NEXT: ptrue p0.d, vl2
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; CHECK-SVE-NEXT: // kill: def $q0 killed $q0 def $z0
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; CHECK-SVE-NEXT: smaxv d0, p0, z0.d
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; CHECK-SVE-NEXT: fmov x0, d0
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; CHECK-SVE-NEXT: ret
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;
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; CHECK-LABEL: smax:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov x8, v0.d[1]
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; CHECK-NEXT: fmov x9, d0
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; CHECK-NEXT: cmp x9, x8
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; CHECK-NEXT: csel x0, x9, x8, gt
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; CHECK-NEXT: ret
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%2 = extractelement <2 x i64> %0, i64 0
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%3 = extractelement <2 x i64> %0, i64 1
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%4 = call i64 @llvm.smax.i64(i64 %2, i64 %3)
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ret i64 %4
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}
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define i64 @umax(<2 x i64> %0) {
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; CHECK-SVE2-LABEL: umax:
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; CHECK-SVE2: // %bb.0:
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; CHECK-SVE2-NEXT: ptrue p0.d, vl2
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; CHECK-SVE2-NEXT: // kill: def $q0 killed $q0 def $z0
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; CHECK-SVE2-NEXT: umaxp z0.d, p0/m, z0.d, z0.d
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; CHECK-SVE2-NEXT: fmov x0, d0
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; CHECK-SVE2-NEXT: ret
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;
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; CHECK-SVE-LABEL: umax:
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; CHECK-SVE: // %bb.0:
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; CHECK-SVE-NEXT: ptrue p0.d, vl2
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; CHECK-SVE-NEXT: // kill: def $q0 killed $q0 def $z0
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; CHECK-SVE-NEXT: umaxv d0, p0, z0.d
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; CHECK-SVE-NEXT: fmov x0, d0
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; CHECK-SVE-NEXT: ret
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;
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; CHECK-LABEL: umax:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov x8, v0.d[1]
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; CHECK-NEXT: fmov x9, d0
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; CHECK-NEXT: cmp x9, x8
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; CHECK-NEXT: csel x0, x9, x8, hi
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; CHECK-NEXT: ret
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%2 = extractelement <2 x i64> %0, i64 0
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%3 = extractelement <2 x i64> %0, i64 1
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%4 = call i64 @llvm.umax.i64(i64 %2, i64 %3)
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ret i64 %4
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}
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define i64 @smin(<2 x i64> %0) {
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; CHECK-SVE2-LABEL: smin:
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; CHECK-SVE2: // %bb.0:
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; CHECK-SVE2-NEXT: ptrue p0.d, vl2
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; CHECK-SVE2-NEXT: // kill: def $q0 killed $q0 def $z0
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; CHECK-SVE2-NEXT: sminp z0.d, p0/m, z0.d, z0.d
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; CHECK-SVE2-NEXT: fmov x0, d0
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; CHECK-SVE2-NEXT: ret
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;
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; CHECK-SVE-LABEL: smin:
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; CHECK-SVE: // %bb.0:
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; CHECK-SVE-NEXT: ptrue p0.d, vl2
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; CHECK-SVE-NEXT: // kill: def $q0 killed $q0 def $z0
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; CHECK-SVE-NEXT: sminv d0, p0, z0.d
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; CHECK-SVE-NEXT: fmov x0, d0
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; CHECK-SVE-NEXT: ret
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;
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; CHECK-LABEL: smin:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov x8, v0.d[1]
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; CHECK-NEXT: fmov x9, d0
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; CHECK-NEXT: cmp x9, x8
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; CHECK-NEXT: csel x0, x9, x8, lt
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; CHECK-NEXT: ret
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%2 = extractelement <2 x i64> %0, i64 0
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%3 = extractelement <2 x i64> %0, i64 1
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%4 = call i64 @llvm.smin.i64(i64 %2, i64 %3)
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ret i64 %4
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}
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define i64 @umin(<2 x i64> %0) {
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; CHECK-SVE2-LABEL: umin:
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; CHECK-SVE2: // %bb.0:
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; CHECK-SVE2-NEXT: ptrue p0.d, vl2
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; CHECK-SVE2-NEXT: // kill: def $q0 killed $q0 def $z0
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; CHECK-SVE2-NEXT: uminp z0.d, p0/m, z0.d, z0.d
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; CHECK-SVE2-NEXT: fmov x0, d0
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; CHECK-SVE2-NEXT: ret
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;
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; CHECK-SVE-LABEL: umin:
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; CHECK-SVE: // %bb.0:
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; CHECK-SVE-NEXT: ptrue p0.d, vl2
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; CHECK-SVE-NEXT: // kill: def $q0 killed $q0 def $z0
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; CHECK-SVE-NEXT: uminv d0, p0, z0.d
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; CHECK-SVE-NEXT: fmov x0, d0
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; CHECK-SVE-NEXT: ret
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;
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; CHECK-LABEL: umin:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov x8, v0.d[1]
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; CHECK-NEXT: fmov x9, d0
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; CHECK-NEXT: cmp x9, x8
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; CHECK-NEXT: csel x0, x9, x8, lo
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; CHECK-NEXT: ret
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%2 = extractelement <2 x i64> %0, i64 0
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%3 = extractelement <2 x i64> %0, i64 1
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%4 = call i64 @llvm.umin.i64(i64 %2, i64 %3)
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ret i64 %4
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}
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define i64 @umin_different_vectors(<2 x i64> %0, <2 x i64> %1) {
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; CHECK-SVE2-LABEL: umin_different_vectors:
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; CHECK-SVE2: // %bb.0:
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; CHECK-SVE2-NEXT: mov x8, v1.d[1]
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; CHECK-SVE2-NEXT: fmov x9, d0
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; CHECK-SVE2-NEXT: cmp x9, x8
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; CHECK-SVE2-NEXT: csel x0, x9, x8, lo
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; CHECK-SVE2-NEXT: ret
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;
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; CHECK-SVE-LABEL: umin_different_vectors:
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; CHECK-SVE: // %bb.0:
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; CHECK-SVE-NEXT: mov x8, v1.d[1]
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; CHECK-SVE-NEXT: fmov x9, d0
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; CHECK-SVE-NEXT: cmp x9, x8
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; CHECK-SVE-NEXT: csel x0, x9, x8, lo
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; CHECK-SVE-NEXT: ret
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;
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; CHECK-LABEL: umin_different_vectors:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov x8, v1.d[1]
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; CHECK-NEXT: fmov x9, d0
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; CHECK-NEXT: cmp x9, x8
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; CHECK-NEXT: csel x0, x9, x8, lo
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; CHECK-NEXT: ret
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%3 = extractelement <2 x i64> %0, i64 0
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%4 = extractelement <2 x i64> %1, i64 1
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%5 = call i64 @llvm.umin.i64(i64 %3, i64 %4)
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ret i64 %5
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}
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