derek.holloway
7502bf64a4
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242 lines
8.9 KiB
LLVM
242 lines
8.9 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=aarch64 < %s | FileCheck %s --check-prefixes=CHECK,CHECK-SD
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; RUN: llc -mtriple=aarch64 -global-isel < %s | FileCheck %s --check-prefixes=CHECK,CHECK-GI
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define <4 x i32> @dup_trunc_sext_v4i32(<4 x i32> %a, <4 x i32> %b, <4 x i32> %x, <4 x i32> %y) {
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; CHECK-SD-LABEL: dup_trunc_sext_v4i32:
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; CHECK-SD: // %bb.0:
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; CHECK-SD-NEXT: cmgt v0.4s, v1.4s, v0.4s
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; CHECK-SD-NEXT: dup v0.4s, v0.s[2]
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; CHECK-SD-NEXT: bsl v0.16b, v2.16b, v3.16b
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: dup_trunc_sext_v4i32:
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; CHECK-GI: // %bb.0:
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; CHECK-GI-NEXT: cmgt v0.4s, v1.4s, v0.4s
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; CHECK-GI-NEXT: mov w8, v0.s[1]
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; CHECK-GI-NEXT: mov w9, v0.s[2]
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; CHECK-GI-NEXT: mov w10, v0.s[3]
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; CHECK-GI-NEXT: mov v0.b[1], w8
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; CHECK-GI-NEXT: mov v0.b[2], w9
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; CHECK-GI-NEXT: mov v0.b[3], w10
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; CHECK-GI-NEXT: dup v0.8b, v0.b[2]
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; CHECK-GI-NEXT: umov w8, v0.b[0]
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; CHECK-GI-NEXT: umov w9, v0.b[1]
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; CHECK-GI-NEXT: fmov s1, w8
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; CHECK-GI-NEXT: umov w8, v0.b[2]
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; CHECK-GI-NEXT: mov v1.s[1], w9
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; CHECK-GI-NEXT: umov w9, v0.b[3]
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; CHECK-GI-NEXT: mov v1.s[2], w8
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; CHECK-GI-NEXT: mov v1.s[3], w9
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; CHECK-GI-NEXT: shl v0.4s, v1.4s, #31
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; CHECK-GI-NEXT: cmlt v0.4s, v0.4s, #0
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; CHECK-GI-NEXT: bsl v0.16b, v2.16b, v3.16b
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; CHECK-GI-NEXT: ret
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%cmp = icmp slt <4 x i32> %a, %b
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%splat = shufflevector <4 x i1> %cmp, <4 x i1> poison, <4 x i32> <i32 2, i32 2, i32 2, i32 2>
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%sel = select <4 x i1> %splat, <4 x i32> %x, <4 x i32> %y
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ret <4 x i32> %sel
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}
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define <2 x i64> @dup_trunc_sext_v2i64(<2 x i64> %a, <2 x i64> %b, <2 x i64> %x, <2 x i64> %y) {
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; CHECK-SD-LABEL: dup_trunc_sext_v2i64:
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; CHECK-SD: // %bb.0:
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; CHECK-SD-NEXT: cmgt v0.2d, v1.2d, v0.2d
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; CHECK-SD-NEXT: dup v0.2d, v0.d[0]
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; CHECK-SD-NEXT: bsl v0.16b, v2.16b, v3.16b
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: dup_trunc_sext_v2i64:
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; CHECK-GI: // %bb.0:
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; CHECK-GI-NEXT: cmgt v0.2d, v1.2d, v0.2d
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; CHECK-GI-NEXT: fmov x9, d0
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; CHECK-GI-NEXT: mov x8, v0.d[1]
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; CHECK-GI-NEXT: fmov s0, w9
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; CHECK-GI-NEXT: mov v0.b[1], w8
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; CHECK-GI-NEXT: dup v0.8b, v0.b[0]
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; CHECK-GI-NEXT: umov w8, v0.b[0]
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; CHECK-GI-NEXT: umov w9, v0.b[1]
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; CHECK-GI-NEXT: fmov d0, x8
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; CHECK-GI-NEXT: mov v0.d[1], x9
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; CHECK-GI-NEXT: shl v0.2d, v0.2d, #63
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; CHECK-GI-NEXT: cmlt v0.2d, v0.2d, #0
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; CHECK-GI-NEXT: bsl v0.16b, v2.16b, v3.16b
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; CHECK-GI-NEXT: ret
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%cmp = icmp slt <2 x i64> %a, %b
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%splat = shufflevector <2 x i1> %cmp, <2 x i1> poison, <2 x i32> <i32 0, i32 0>
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%sel = select <2 x i1> %splat, <2 x i64> %x, <2 x i64> %y
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ret <2 x i64> %sel
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}
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define <4 x float> @dup_trunc_sext_v4f32(<4 x float> %a, <4 x float> %b, <4 x float> %x, <4 x float> %y) {
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; CHECK-SD-LABEL: dup_trunc_sext_v4f32:
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; CHECK-SD: // %bb.0:
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; CHECK-SD-NEXT: fcmge v0.4s, v1.4s, v0.4s
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; CHECK-SD-NEXT: dup v0.4s, v0.s[3]
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; CHECK-SD-NEXT: bsl v0.16b, v2.16b, v3.16b
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: dup_trunc_sext_v4f32:
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; CHECK-GI: // %bb.0:
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; CHECK-GI-NEXT: fcmge v0.4s, v1.4s, v0.4s
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; CHECK-GI-NEXT: mov w8, v0.s[1]
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; CHECK-GI-NEXT: mov w9, v0.s[2]
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; CHECK-GI-NEXT: mov w10, v0.s[3]
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; CHECK-GI-NEXT: mov v0.b[1], w8
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; CHECK-GI-NEXT: mov v0.b[2], w9
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; CHECK-GI-NEXT: mov v0.b[3], w10
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; CHECK-GI-NEXT: dup v0.8b, v0.b[3]
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; CHECK-GI-NEXT: umov w8, v0.b[0]
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; CHECK-GI-NEXT: umov w9, v0.b[1]
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; CHECK-GI-NEXT: fmov s1, w8
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; CHECK-GI-NEXT: umov w8, v0.b[2]
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; CHECK-GI-NEXT: mov v1.s[1], w9
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; CHECK-GI-NEXT: umov w9, v0.b[3]
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; CHECK-GI-NEXT: mov v1.s[2], w8
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; CHECK-GI-NEXT: mov v1.s[3], w9
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; CHECK-GI-NEXT: shl v0.4s, v1.4s, #31
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; CHECK-GI-NEXT: cmlt v0.4s, v0.4s, #0
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; CHECK-GI-NEXT: bsl v0.16b, v2.16b, v3.16b
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; CHECK-GI-NEXT: ret
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%cmp = fcmp ole <4 x float> %a, %b
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%splat = shufflevector <4 x i1> %cmp, <4 x i1> poison, <4 x i32> <i32 3, i32 3, i32 3, i32 3>
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%sel = select <4 x i1> %splat, <4 x float> %x, <4 x float> %y
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ret <4 x float> %sel
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}
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define <2 x double> @dup_trunc_sext_v2f64(<2 x double> %a, <2 x double> %b, <2 x double> %x, <2 x double> %y) {
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; CHECK-SD-LABEL: dup_trunc_sext_v2f64:
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; CHECK-SD: // %bb.0:
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; CHECK-SD-NEXT: fcmge v0.2d, v1.2d, v0.2d
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; CHECK-SD-NEXT: dup v0.2d, v0.d[1]
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; CHECK-SD-NEXT: bsl v0.16b, v2.16b, v3.16b
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: dup_trunc_sext_v2f64:
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; CHECK-GI: // %bb.0:
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; CHECK-GI-NEXT: fcmge v0.2d, v1.2d, v0.2d
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; CHECK-GI-NEXT: fmov x9, d0
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; CHECK-GI-NEXT: mov x8, v0.d[1]
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; CHECK-GI-NEXT: fmov s0, w9
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; CHECK-GI-NEXT: mov v0.b[1], w8
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; CHECK-GI-NEXT: dup v0.8b, v0.b[1]
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; CHECK-GI-NEXT: umov w8, v0.b[0]
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; CHECK-GI-NEXT: umov w9, v0.b[1]
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; CHECK-GI-NEXT: fmov d0, x8
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; CHECK-GI-NEXT: mov v0.d[1], x9
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; CHECK-GI-NEXT: shl v0.2d, v0.2d, #63
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; CHECK-GI-NEXT: cmlt v0.2d, v0.2d, #0
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; CHECK-GI-NEXT: bsl v0.16b, v2.16b, v3.16b
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; CHECK-GI-NEXT: ret
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%cmp = fcmp ole <2 x double> %a, %b
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%splat = shufflevector <2 x i1> %cmp, <2 x i1> poison, <2 x i32> <i32 1, i32 1>
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%sel = select <2 x i1> %splat, <2 x double> %x, <2 x double> %y
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ret <2 x double> %sel
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}
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define <4 x i32> @dup_trunc_sext_v4i32_idx0(<4 x i32> %a, <4 x i32> %b, <4 x i32> %x, <4 x i32> %y) {
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; CHECK-SD-LABEL: dup_trunc_sext_v4i32_idx0:
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; CHECK-SD: // %bb.0:
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; CHECK-SD-NEXT: cmgt v0.4s, v1.4s, v0.4s
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; CHECK-SD-NEXT: dup v0.4s, v0.s[0]
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; CHECK-SD-NEXT: bsl v0.16b, v2.16b, v3.16b
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: dup_trunc_sext_v4i32_idx0:
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; CHECK-GI: // %bb.0:
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; CHECK-GI-NEXT: cmgt v0.4s, v1.4s, v0.4s
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; CHECK-GI-NEXT: mov w8, v0.s[1]
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; CHECK-GI-NEXT: mov w9, v0.s[2]
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; CHECK-GI-NEXT: mov w10, v0.s[3]
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; CHECK-GI-NEXT: mov v0.b[1], w8
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; CHECK-GI-NEXT: mov v0.b[2], w9
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; CHECK-GI-NEXT: mov v0.b[3], w10
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; CHECK-GI-NEXT: dup v0.8b, v0.b[0]
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; CHECK-GI-NEXT: umov w8, v0.b[0]
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; CHECK-GI-NEXT: umov w9, v0.b[1]
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; CHECK-GI-NEXT: fmov s1, w8
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; CHECK-GI-NEXT: umov w8, v0.b[2]
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; CHECK-GI-NEXT: mov v1.s[1], w9
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; CHECK-GI-NEXT: umov w9, v0.b[3]
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; CHECK-GI-NEXT: mov v1.s[2], w8
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; CHECK-GI-NEXT: mov v1.s[3], w9
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; CHECK-GI-NEXT: shl v0.4s, v1.4s, #31
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; CHECK-GI-NEXT: cmlt v0.4s, v0.4s, #0
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; CHECK-GI-NEXT: bsl v0.16b, v2.16b, v3.16b
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; CHECK-GI-NEXT: ret
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%cmp = icmp slt <4 x i32> %a, %b
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%splat = shufflevector <4 x i1> %cmp, <4 x i1> poison, <4 x i32> zeroinitializer
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%sel = select <4 x i1> %splat, <4 x i32> %x, <4 x i32> %y
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ret <4 x i32> %sel
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}
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define <8 x i16> @dup_trunc_sext_v8i16(<8 x i16> %a, <8 x i16> %b, <8 x i16> %x, <8 x i16> %y) {
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; CHECK-SD-LABEL: dup_trunc_sext_v8i16:
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; CHECK-SD: // %bb.0:
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; CHECK-SD-NEXT: cmgt v0.8h, v1.8h, v0.8h
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; CHECK-SD-NEXT: dup v0.8h, v0.h[2]
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; CHECK-SD-NEXT: bsl v0.16b, v2.16b, v3.16b
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: dup_trunc_sext_v8i16:
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; CHECK-GI: // %bb.0:
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; CHECK-GI-NEXT: cmgt v0.8h, v1.8h, v0.8h
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; CHECK-GI-NEXT: xtn v0.8b, v0.8h
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; CHECK-GI-NEXT: dup v0.8b, v0.b[2]
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; CHECK-GI-NEXT: ushll v0.8h, v0.8b, #0
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; CHECK-GI-NEXT: shl v0.8h, v0.8h, #15
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; CHECK-GI-NEXT: cmlt v0.8h, v0.8h, #0
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; CHECK-GI-NEXT: bsl v0.16b, v2.16b, v3.16b
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; CHECK-GI-NEXT: ret
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%cmp = icmp slt <8 x i16> %a, %b
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%splat = shufflevector <8 x i1> %cmp, <8 x i1> poison, <8 x i32> <i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2>
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%sel = select <8 x i1> %splat, <8 x i16> %x, <8 x i16> %y
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ret <8 x i16> %sel
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}
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define <2 x i64> @negative_sext_i32(<2 x i64> %mask) {
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; CHECK-LABEL: negative_sext_i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: xtn v0.2s, v0.2d
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; CHECK-NEXT: dup v0.2s, v0.s[1]
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; CHECK-NEXT: sshll v0.2d, v0.2s, #0
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; CHECK-NEXT: ret
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%trunc = trunc <2 x i64> %mask to <2 x i32>
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%splat = shufflevector <2 x i32> %trunc, <2 x i32> poison, <2 x i32> <i32 1, i32 1>
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%ext = sext <2 x i32> %splat to <2 x i64>
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ret <2 x i64> %ext
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}
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define <2 x i64> @dup_trunc_zext_i32(<2 x i64> %a) {
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; CHECK-SD-LABEL: dup_trunc_zext_i32:
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; CHECK-SD: // %bb.0:
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; CHECK-SD-NEXT: ushr v0.2d, v0.2d, #32
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; CHECK-SD-NEXT: dup v0.2d, v0.d[1]
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; CHECK-SD-NEXT: ret
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;
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; CHECK-GI-LABEL: dup_trunc_zext_i32:
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; CHECK-GI: // %bb.0:
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; CHECK-GI-NEXT: shrn v0.2s, v0.2d, #32
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; CHECK-GI-NEXT: dup v0.2s, v0.s[1]
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; CHECK-GI-NEXT: ushll v0.2d, v0.2s, #0
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; CHECK-GI-NEXT: ret
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%shifted = lshr <2 x i64> %a, <i64 32, i64 32>
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%trunc = trunc <2 x i64> %shifted to <2 x i32>
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%splat = shufflevector <2 x i32> %trunc, <2 x i32> poison, <2 x i32> <i32 1, i32 1>
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%ext = zext <2 x i32> %splat to <2 x i64>
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ret <2 x i64> %ext
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}
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define <2 x i64> @negative_zext_i32(<2 x i64> %mask) {
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; CHECK-LABEL: negative_zext_i32:
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; CHECK: // %bb.0:
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; CHECK-NEXT: xtn v0.2s, v0.2d
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; CHECK-NEXT: dup v0.2s, v0.s[1]
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; CHECK-NEXT: ushll v0.2d, v0.2s, #0
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; CHECK-NEXT: ret
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%trunc = trunc <2 x i64> %mask to <2 x i32>
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%splat = shufflevector <2 x i32> %trunc, <2 x i32> poison, <2 x i32> <i32 1, i32 1>
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%ext = zext <2 x i32> %splat to <2 x i64>
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ret <2 x i64> %ext
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}
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