derek.holloway
7502bf64a4
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306 lines
9.2 KiB
LLVM
306 lines
9.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=aarch64 -mattr=+sve < %s | FileCheck %s
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; This tests that various ands, sexts, and zexts (and other operations)
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; operating on vscale or the SVE count instructions can be eliminated
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; (via demanded bits) due to their known limited range.
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; On AArch64 vscale can be at most 16 (for a 2048-bit vector).
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; The counting instructions (sans multiplier) have a value of at most 256
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; (for a 2048-bit vector of i8s).
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define i32 @vscale_and_elimination() vscale_range(1,16) {
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; CHECK-LABEL: vscale_and_elimination:
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; CHECK: // %bb.0:
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; CHECK-NEXT: rdvl x8, #1
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; CHECK-NEXT: lsr x8, x8, #4
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; CHECK-NEXT: and w9, w8, #0x1c
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; CHECK-NEXT: add w0, w8, w9
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; CHECK-NEXT: ret
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%vscale = call i32 @llvm.vscale.i32()
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%and_redundant = and i32 %vscale, 31
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%and_required = and i32 %vscale, 17179869180
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%result = add i32 %and_redundant, %and_required
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ret i32 %result
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}
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define i64 @cntb_and_elimination() {
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; CHECK-LABEL: cntb_and_elimination:
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; CHECK: // %bb.0:
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; CHECK-NEXT: cntb x8
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; CHECK-NEXT: and x9, x8, #0x1fc
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; CHECK-NEXT: add x0, x8, x9
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; CHECK-NEXT: ret
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%cntb = call i64 @llvm.aarch64.sve.cntb(i32 31)
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%and_redundant = and i64 %cntb, 511
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%and_required = and i64 %cntb, 17179869180
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%result = add i64 %and_redundant, %and_required
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ret i64 %result
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}
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define i64 @cnth_and_elimination() {
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; CHECK-LABEL: cnth_and_elimination:
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; CHECK: // %bb.0:
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; CHECK-NEXT: cnth x8
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; CHECK-NEXT: and x9, x8, #0xfc
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; CHECK-NEXT: add x0, x8, x9
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; CHECK-NEXT: ret
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%cnth = call i64 @llvm.aarch64.sve.cnth(i32 31)
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%and_redundant = and i64 %cnth, 1023
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%and_required = and i64 %cnth, 17179869180
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%result = add i64 %and_redundant, %and_required
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ret i64 %result
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}
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define i64 @cntw_and_elimination() {
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; CHECK-LABEL: cntw_and_elimination:
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; CHECK: // %bb.0:
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; CHECK-NEXT: cntw x8
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; CHECK-NEXT: and x9, x8, #0x7c
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; CHECK-NEXT: add x0, x8, x9
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; CHECK-NEXT: ret
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%cntw = call i64 @llvm.aarch64.sve.cntw(i32 31)
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%and_redundant = and i64 %cntw, 127
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%and_required = and i64 %cntw, 17179869180
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%result = add i64 %and_redundant, %and_required
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ret i64 %result
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}
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define i64 @cntd_and_elimination() {
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; CHECK-LABEL: cntd_and_elimination:
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; CHECK: // %bb.0:
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; CHECK-NEXT: cntd x8
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; CHECK-NEXT: and x9, x8, #0x3c
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; CHECK-NEXT: add x0, x8, x9
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; CHECK-NEXT: ret
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%cntd = call i64 @llvm.aarch64.sve.cntd(i32 31)
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%and_redundant = and i64 %cntd, 63
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%and_required = and i64 %cntd, 17179869180
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%result = add i64 %and_redundant, %and_required
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ret i64 %result
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}
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define i64 @cntp_nxv16i1_and_elimination(<vscale x 16 x i1> %p) {
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; CHECK-LABEL: cntp_nxv16i1_and_elimination:
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; CHECK: // %bb.0:
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; CHECK-NEXT: cntp x8, p0, p0.b
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; CHECK-NEXT: and x9, x8, #0x1fc
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; CHECK-NEXT: add x0, x8, x9
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; CHECK-NEXT: ret
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%cntp = tail call i64 @llvm.aarch64.sve.cntp.nxv16i1(<vscale x 16 x i1> %p, <vscale x 16 x i1> %p)
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%and_redundant = and i64 %cntp, 511
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%and_required = and i64 %cntp, 17179869180
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%result = add i64 %and_redundant, %and_required
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ret i64 %result
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}
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define i64 @cntp_nxv8i1_and_elimination(<vscale x 8 x i1> %p) {
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; CHECK-LABEL: cntp_nxv8i1_and_elimination:
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; CHECK: // %bb.0:
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; CHECK-NEXT: cntp x8, p0, p0.h
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; CHECK-NEXT: and x9, x8, #0xfc
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; CHECK-NEXT: add x0, x8, x9
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; CHECK-NEXT: ret
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%cntp = tail call i64 @llvm.aarch64.sve.cntp.nxv8i1(<vscale x 8 x i1> %p, <vscale x 8 x i1> %p)
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%and_redundant = and i64 %cntp, 1023
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%and_required = and i64 %cntp, 17179869180
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%result = add i64 %and_redundant, %and_required
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ret i64 %result
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}
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define i64 @cntp_nxv4i1_and_elimination(<vscale x 4 x i1> %p) {
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; CHECK-LABEL: cntp_nxv4i1_and_elimination:
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; CHECK: // %bb.0:
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; CHECK-NEXT: cntp x8, p0, p0.s
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; CHECK-NEXT: and x9, x8, #0x7c
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; CHECK-NEXT: add x0, x8, x9
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; CHECK-NEXT: ret
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%cntp = tail call i64 @llvm.aarch64.sve.cntp.nxv4i1(<vscale x 4 x i1> %p, <vscale x 4 x i1> %p)
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%and_redundant = and i64 %cntp, 127
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%and_required = and i64 %cntp, 17179869180
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%result = add i64 %and_redundant, %and_required
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ret i64 %result
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}
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define i64 @cntp_nxv2i1_and_elimination(<vscale x 2 x i1> %p) {
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; CHECK-LABEL: cntp_nxv2i1_and_elimination:
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; CHECK: // %bb.0:
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; CHECK-NEXT: cntp x8, p0, p0.d
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; CHECK-NEXT: and x9, x8, #0x3c
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; CHECK-NEXT: add x0, x8, x9
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; CHECK-NEXT: ret
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%cntp = tail call i64 @llvm.aarch64.sve.cntp.nxv2i1(<vscale x 2 x i1> %p, <vscale x 2 x i1> %p)
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%and_redundant = and i64 %cntp, 63
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%and_required = and i64 %cntp, 17179869180
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%result = add i64 %and_redundant, %and_required
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ret i64 %result
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}
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define i64 @vscale_trunc_zext() vscale_range(1,16) {
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; CHECK-LABEL: vscale_trunc_zext:
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; CHECK: // %bb.0:
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; CHECK-NEXT: rdvl x8, #1
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; CHECK-NEXT: lsr x0, x8, #4
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; CHECK-NEXT: ret
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%vscale = call i32 @llvm.vscale.i32()
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%zext = zext i32 %vscale to i64
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ret i64 %zext
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}
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define i64 @vscale_trunc_sext() vscale_range(1,16) {
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; CHECK-LABEL: vscale_trunc_sext:
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; CHECK: // %bb.0:
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; CHECK-NEXT: rdvl x8, #1
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; CHECK-NEXT: lsr x0, x8, #4
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; CHECK-NEXT: ret
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%vscale = call i32 @llvm.vscale.i32()
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%sext = sext i32 %vscale to i64
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ret i64 %sext
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}
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define i64 @count_bytes_trunc_zext() {
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; CHECK-LABEL: count_bytes_trunc_zext:
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; CHECK: // %bb.0:
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; CHECK-NEXT: cntb x0
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; CHECK-NEXT: ret
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%cnt = call i64 @llvm.aarch64.sve.cntb(i32 31)
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%trunc = trunc i64 %cnt to i32
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%zext = zext i32 %trunc to i64
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ret i64 %zext
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}
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define i64 @count_halfs_trunc_zext() {
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; CHECK-LABEL: count_halfs_trunc_zext:
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; CHECK: // %bb.0:
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; CHECK-NEXT: cnth x0
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; CHECK-NEXT: ret
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%cnt = call i64 @llvm.aarch64.sve.cnth(i32 31)
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%trunc = trunc i64 %cnt to i32
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%zext = zext i32 %trunc to i64
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ret i64 %zext
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}
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define i64 @count_words_trunc_zext() {
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; CHECK-LABEL: count_words_trunc_zext:
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; CHECK: // %bb.0:
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; CHECK-NEXT: cntw x0
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; CHECK-NEXT: ret
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%cnt = call i64 @llvm.aarch64.sve.cntw(i32 31)
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%trunc = trunc i64 %cnt to i32
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%zext = zext i32 %trunc to i64
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ret i64 %zext
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}
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define i64 @count_doubles_trunc_zext() {
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; CHECK-LABEL: count_doubles_trunc_zext:
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; CHECK: // %bb.0:
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; CHECK-NEXT: cntd x0
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; CHECK-NEXT: ret
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%cnt = call i64 @llvm.aarch64.sve.cntd(i32 31)
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%trunc = trunc i64 %cnt to i32
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%zext = zext i32 %trunc to i64
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ret i64 %zext
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}
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define i64 @count_bytes_trunc_sext() {
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; CHECK-LABEL: count_bytes_trunc_sext:
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; CHECK: // %bb.0:
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; CHECK-NEXT: cntb x0
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; CHECK-NEXT: ret
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%cnt = call i64 @llvm.aarch64.sve.cntb(i32 31)
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%trunc = trunc i64 %cnt to i32
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%sext = sext i32 %trunc to i64
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ret i64 %sext
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}
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define i64 @count_halfs_trunc_sext() {
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; CHECK-LABEL: count_halfs_trunc_sext:
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; CHECK: // %bb.0:
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; CHECK-NEXT: cnth x0
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; CHECK-NEXT: ret
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%cnt = call i64 @llvm.aarch64.sve.cnth(i32 31)
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%trunc = trunc i64 %cnt to i32
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%sext = sext i32 %trunc to i64
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ret i64 %sext
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}
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define i64 @count_words_trunc_sext() {
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; CHECK-LABEL: count_words_trunc_sext:
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; CHECK: // %bb.0:
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; CHECK-NEXT: cntw x0
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; CHECK-NEXT: ret
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%cnt = call i64 @llvm.aarch64.sve.cntw(i32 31)
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%trunc = trunc i64 %cnt to i32
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%sext = sext i32 %trunc to i64
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ret i64 %sext
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}
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define i64 @count_doubles_trunc_sext() {
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; CHECK-LABEL: count_doubles_trunc_sext:
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; CHECK: // %bb.0:
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; CHECK-NEXT: cntd x0
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; CHECK-NEXT: ret
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%cnt = call i64 @llvm.aarch64.sve.cntd(i32 31)
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%trunc = trunc i64 %cnt to i32
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%sext = sext i32 %trunc to i64
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ret i64 %sext
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}
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define i32 @vscale_with_multiplier() vscale_range(1,16) {
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; CHECK-LABEL: vscale_with_multiplier:
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; CHECK: // %bb.0:
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; CHECK-NEXT: rdvl x8, #1
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; CHECK-NEXT: mov w9, #5 // =0x5
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; CHECK-NEXT: lsr x8, x8, #4
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; CHECK-NEXT: mul x8, x8, x9
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; CHECK-NEXT: and w9, w8, #0x3f
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; CHECK-NEXT: add w0, w8, w9
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; CHECK-NEXT: ret
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%vscale = call i32 @llvm.vscale.i32()
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%mul = mul i32 %vscale, 5
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%and_redundant = and i32 %mul, 127
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%and_required = and i32 %mul, 63
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%result = add i32 %and_redundant, %and_required
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ret i32 %result
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}
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define i32 @vscale_with_negative_multiplier() vscale_range(1,16) {
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; CHECK-LABEL: vscale_with_negative_multiplier:
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; CHECK: // %bb.0:
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; CHECK-NEXT: rdvl x8, #1
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; CHECK-NEXT: mov x9, #-5 // =0xfffffffffffffffb
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; CHECK-NEXT: lsr x8, x8, #4
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; CHECK-NEXT: mul x8, x8, x9
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; CHECK-NEXT: and w9, w8, #0xffffffc0
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; CHECK-NEXT: add w0, w8, w9
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; CHECK-NEXT: ret
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%vscale = call i32 @llvm.vscale.i32()
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%mul = mul i32 %vscale, -5
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%or_redundant = or i32 %mul, 4294967168
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%or_required = and i32 %mul, 4294967232
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%result = add i32 %or_redundant, %or_required
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ret i32 %result
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}
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define i32 @pow2_vscale_with_negative_multiplier() vscale_range(1,16) {
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; CHECK-LABEL: pow2_vscale_with_negative_multiplier:
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; CHECK: // %bb.0:
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; CHECK-NEXT: cntd x8
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; CHECK-NEXT: neg x9, x8
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; CHECK-NEXT: orr w9, w9, #0xfffffff0
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; CHECK-NEXT: sub w0, w9, w8
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; CHECK-NEXT: ret
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%vscale = call i32 @llvm.vscale.i32()
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%mul = mul i32 %vscale, -2
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%or_redundant = or i32 %mul, 4294967264
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%or_required = or i32 %mul, 4294967280
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%result = add i32 %or_redundant, %or_required
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ret i32 %result
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}
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declare i32 @llvm.vscale.i32()
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declare i64 @llvm.aarch64.sve.cntb(i32 %pattern)
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declare i64 @llvm.aarch64.sve.cnth(i32 %pattern)
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declare i64 @llvm.aarch64.sve.cntw(i32 %pattern)
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declare i64 @llvm.aarch64.sve.cntd(i32 %pattern)
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