derek.holloway
7502bf64a4
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205 lines
6.3 KiB
YAML
205 lines
6.3 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=amdgcn-amd-amdhsa -run-pass=amdgpu-postlegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s
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---
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name: narrow_lshr_s64_32_s64amt
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1
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; CHECK-LABEL: name: narrow_lshr_s64_32_s64amt
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; CHECK: liveins: $vgpr0_vgpr1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
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; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)
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; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[UV1]](s32)
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; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[ZEXT]](s64)
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%0:_(s64) = COPY $vgpr0_vgpr1
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%1:_(s64) = G_CONSTANT i64 32
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%2:_(s64) = G_LSHR %0, %1
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$vgpr0_vgpr1 = COPY %2
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...
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---
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name: narrow_lshr_s64_32
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1
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; CHECK-LABEL: name: narrow_lshr_s64_32
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; CHECK: liveins: $vgpr0_vgpr1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
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; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)
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; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[UV1]](s32)
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; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[ZEXT]](s64)
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%0:_(s64) = COPY $vgpr0_vgpr1
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%1:_(s32) = G_CONSTANT i32 32
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%2:_(s64) = G_LSHR %0, %1
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$vgpr0_vgpr1 = COPY %2
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...
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---
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name: narrow_lshr_s64_33
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1
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; CHECK-LABEL: name: narrow_lshr_s64_33
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; CHECK: liveins: $vgpr0_vgpr1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
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; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)
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; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
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; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C]](s32)
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; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[LSHR]](s32)
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; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[ZEXT]](s64)
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%0:_(s64) = COPY $vgpr0_vgpr1
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%1:_(s32) = G_CONSTANT i32 33
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%2:_(s64) = G_LSHR %0, %1
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$vgpr0_vgpr1 = COPY %2
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...
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---
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name: narrow_lshr_s64_31
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1
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; CHECK-LABEL: name: narrow_lshr_s64_31
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; CHECK: liveins: $vgpr0_vgpr1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
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; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
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; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s64) = G_LSHR [[COPY]], [[C]](s32)
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; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[LSHR]](s64)
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%0:_(s64) = COPY $vgpr0_vgpr1
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%1:_(s32) = G_CONSTANT i32 31
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%2:_(s64) = G_LSHR %0, %1
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$vgpr0_vgpr1 = COPY %2
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...
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---
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name: narrow_lshr_s64_63
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1
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; CHECK-LABEL: name: narrow_lshr_s64_63
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; CHECK: liveins: $vgpr0_vgpr1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
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; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)
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; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
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; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[UV1]], [[C]](s32)
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; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[LSHR]](s32)
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; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[ZEXT]](s64)
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%0:_(s64) = COPY $vgpr0_vgpr1
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%1:_(s32) = G_CONSTANT i32 63
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%2:_(s64) = G_LSHR %0, %1
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$vgpr0_vgpr1 = COPY %2
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...
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---
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name: narrow_lshr_s64_64
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1
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; CHECK-LABEL: name: narrow_lshr_s64_64
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; CHECK: liveins: $vgpr0_vgpr1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
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; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[DEF]](s64)
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%0:_(s64) = COPY $vgpr0_vgpr1
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%1:_(s32) = G_CONSTANT i32 64
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%2:_(s64) = G_LSHR %0, %1
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$vgpr0_vgpr1 = COPY %2
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...
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---
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name: narrow_lshr_s64_65
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1
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; CHECK-LABEL: name: narrow_lshr_s64_65
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; CHECK: liveins: $vgpr0_vgpr1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
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; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[DEF]](s64)
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%0:_(s64) = COPY $vgpr0_vgpr1
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%1:_(s32) = G_CONSTANT i32 65
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%2:_(s64) = G_LSHR %0, %1
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$vgpr0_vgpr1 = COPY %2
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...
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---
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name: narrow_lshr_s32_16
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0
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; CHECK-LABEL: name: narrow_lshr_s32_16
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; CHECK: liveins: $vgpr0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
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; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
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; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32)
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; CHECK-NEXT: $vgpr0 = COPY [[LSHR]](s32)
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%0:_(s32) = COPY $vgpr0
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%1:_(s32) = G_CONSTANT i32 16
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%2:_(s32) = G_LSHR %0, %1
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$vgpr0 = COPY %2
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...
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---
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name: narrow_lshr_s32_17
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0
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; CHECK-LABEL: name: narrow_lshr_s32_17
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; CHECK: liveins: $vgpr0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
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; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 17
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; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32)
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; CHECK-NEXT: $vgpr0 = COPY [[LSHR]](s32)
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%0:_(s32) = COPY $vgpr0
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%1:_(s32) = G_CONSTANT i32 17
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%2:_(s32) = G_LSHR %0, %1
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$vgpr0 = COPY %2
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...
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---
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name: narrow_lshr_v2s32_17
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1
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; CHECK-LABEL: name: narrow_lshr_v2s32_17
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; CHECK: liveins: $vgpr0_vgpr1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
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; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 17
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; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32)
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; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(<2 x s32>) = G_LSHR [[COPY]], [[BUILD_VECTOR]](<2 x s32>)
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; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[LSHR]](<2 x s32>)
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%0:_(<2 x s32>) = COPY $vgpr0_vgpr1
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%1:_(s32) = G_CONSTANT i32 17
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%2:_(<2 x s32>) = G_BUILD_VECTOR %1, %1
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%3:_(<2 x s32>) = G_LSHR %0, %2
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$vgpr0_vgpr1 = COPY %3
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...
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