derek.holloway
7502bf64a4
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165 lines
5.1 KiB
YAML
165 lines
5.1 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1030 -run-pass=amdgpu-regbank-combiner %s -o - | FileCheck %s
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---
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name: inreg8_inreg16
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0
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; CHECK-LABEL: name: inreg8_inreg16
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; CHECK: liveins: $vgpr0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: %copy:_(s32) = COPY $vgpr0
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; CHECK-NEXT: %inreg:_(s32) = G_SEXT_INREG %copy, 8
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; CHECK-NEXT: $vgpr0 = COPY %inreg(s32)
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%copy:_(s32) = COPY $vgpr0
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%inreg:_(s32) = G_SEXT_INREG %copy, 8
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%inreg1:_(s32) = G_SEXT_INREG %inreg, 16
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$vgpr0 = COPY %inreg1
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...
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---
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name: inreg16_inreg16
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0
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; CHECK-LABEL: name: inreg16_inreg16
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; CHECK: liveins: $vgpr0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: %copy:_(s32) = COPY $vgpr0
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; CHECK-NEXT: %inreg:_(s32) = G_SEXT_INREG %copy, 16
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; CHECK-NEXT: $vgpr0 = COPY %inreg(s32)
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%copy:_(s32) = COPY $vgpr0
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%inreg:_(s32) = G_SEXT_INREG %copy, 16
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%inreg1:_(s32) = G_SEXT_INREG %inreg, 16
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$vgpr0 = COPY %inreg1
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...
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---
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name: inreg16_inreg8
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0
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; CHECK-LABEL: name: inreg16_inreg8
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; CHECK: liveins: $vgpr0
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: %copy:_(s32) = COPY $vgpr0
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; CHECK-NEXT: %inreg1:_(s32) = G_SEXT_INREG %copy, 8
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; CHECK-NEXT: $vgpr0 = COPY %inreg1(s32)
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%copy:_(s32) = COPY $vgpr0
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%inreg:_(s32) = G_SEXT_INREG %copy, 16
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%inreg1:_(s32) = G_SEXT_INREG %inreg, 8
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$vgpr0 = COPY %inreg1
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...
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---
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name: inreg16_inreg32_64bit
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1
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; CHECK-LABEL: name: inreg16_inreg32_64bit
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; CHECK: liveins: $vgpr0_vgpr1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: %copy:_(s64) = COPY $vgpr0_vgpr1
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; CHECK-NEXT: %inreg:_(s64) = G_SEXT_INREG %copy, 16
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; CHECK-NEXT: $vgpr0_vgpr1 = COPY %inreg(s64)
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%copy:_(s64) = COPY $vgpr0_vgpr1
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%inreg:_(s64) = G_SEXT_INREG %copy, 16
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%inreg1:_(s64) = G_SEXT_INREG %inreg, 32
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$vgpr0_vgpr1 = COPY %inreg1
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...
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---
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name: inreg32_inreg32_64bit
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1
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; CHECK-LABEL: name: inreg32_inreg32_64bit
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; CHECK: liveins: $vgpr0_vgpr1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: %copy:_(s64) = COPY $vgpr0_vgpr1
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; CHECK-NEXT: %inreg:_(s64) = G_SEXT_INREG %copy, 32
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; CHECK-NEXT: $vgpr0_vgpr1 = COPY %inreg(s64)
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%copy:_(s64) = COPY $vgpr0_vgpr1
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%inreg:_(s64) = G_SEXT_INREG %copy, 32
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%inreg1:_(s64) = G_SEXT_INREG %inreg, 32
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$vgpr0_vgpr1 = COPY %inreg1
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...
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---
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name: inreg32_inreg16_64bit
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1
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; CHECK-LABEL: name: inreg32_inreg16_64bit
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; CHECK: liveins: $vgpr0_vgpr1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: %copy:_(s64) = COPY $vgpr0_vgpr1
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; CHECK-NEXT: %inreg1:_(s64) = G_SEXT_INREG %copy, 16
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; CHECK-NEXT: $vgpr0_vgpr1 = COPY %inreg1(s64)
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%copy:_(s64) = COPY $vgpr0_vgpr1
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%inreg:_(s64) = G_SEXT_INREG %copy, 32
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%inreg1:_(s64) = G_SEXT_INREG %inreg, 16
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$vgpr0_vgpr1 = COPY %inreg1
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...
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---
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name: vector_inreg8_inreg16
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1_vgpr2_vgpr3
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; CHECK-LABEL: name: vector_inreg8_inreg16
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; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: %copy:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
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; CHECK-NEXT: %inreg:_(<4 x s32>) = G_SEXT_INREG %copy, 8
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; CHECK-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY %inreg(<4 x s32>)
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%copy:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
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%inreg:_(<4 x s32>) = G_SEXT_INREG %copy, 8
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%inreg1:_(<4 x s32>) = G_SEXT_INREG %inreg, 16
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$vgpr0_vgpr1_vgpr2_vgpr3 = COPY %inreg1
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...
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---
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name: vector_inreg16_inreg16
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1_vgpr2_vgpr3
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; CHECK-LABEL: name: vector_inreg16_inreg16
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; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: %copy:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
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; CHECK-NEXT: %inreg:_(<4 x s32>) = G_SEXT_INREG %copy, 16
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; CHECK-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY %inreg(<4 x s32>)
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%copy:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
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%inreg:_(<4 x s32>) = G_SEXT_INREG %copy, 16
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%inreg1:_(<4 x s32>) = G_SEXT_INREG %inreg, 16
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$vgpr0_vgpr1_vgpr2_vgpr3 = COPY %inreg1
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...
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---
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name: vector_inreg16_inreg8
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0_vgpr1_vgpr2_vgpr3
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; CHECK-LABEL: name: vector_inreg16_inreg8
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; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: %copy:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
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; CHECK-NEXT: %inreg1:_(<4 x s32>) = G_SEXT_INREG %copy, 8
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; CHECK-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY %inreg1(<4 x s32>)
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%copy:_(<4 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3
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%inreg:_(<4 x s32>) = G_SEXT_INREG %copy, 16
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%inreg1:_(<4 x s32>) = G_SEXT_INREG %inreg, 8
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$vgpr0_vgpr1_vgpr2_vgpr3 = COPY %inreg1
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...
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