derek.holloway
7502bf64a4
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209 lines
6.9 KiB
YAML
209 lines
6.9 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=amdgcn -run-pass=amdgpu-prelegalizer-combiner %s -o - | FileCheck %s
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---
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name: combine_ashr
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1, $vgpr31
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liveins: $vgpr0, $vgpr1
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; CHECK-LABEL: name: combine_ashr
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; CHECK: liveins: $vgpr0, $vgpr1, $vgpr31, $vgpr0, $vgpr1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
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; CHECK-NEXT: [[MV:%[0-9]+]]:_(p0) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)
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; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
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; CHECK-NEXT: G_STORE [[C]](s32), [[MV]](p0) :: (store (s32))
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; CHECK-NEXT: SI_RETURN
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%0:_(s32) = COPY $vgpr0
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%1:_(s32) = COPY $vgpr1
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%2:_(p0) = G_MERGE_VALUES %0(s32), %1(s32)
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%3:_(s32) = G_CONSTANT i32 10
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%4:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.workitem.id.x)
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%5:_(s32) = G_ASHR %4, %3(s32)
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G_STORE %5(s32), %2(p0) :: (store (s32))
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SI_RETURN
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...
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---
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name: combine_lshr
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1, $vgpr31
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liveins: $vgpr0, $vgpr1
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; CHECK-LABEL: name: combine_lshr
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; CHECK: liveins: $vgpr0, $vgpr1, $vgpr31, $vgpr0, $vgpr1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
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; CHECK-NEXT: [[MV:%[0-9]+]]:_(p0) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)
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; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
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; CHECK-NEXT: G_STORE [[C]](s32), [[MV]](p0) :: (store (s32))
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; CHECK-NEXT: SI_RETURN
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%0:_(s32) = COPY $vgpr0
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%1:_(s32) = COPY $vgpr1
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%2:_(p0) = G_MERGE_VALUES %0(s32), %1(s32)
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%3:_(s32) = G_CONSTANT i32 10
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%4:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.workitem.id.x)
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%5:_(s32) = G_LSHR %4, %3(s32)
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G_STORE %5(s32), %2(p0) :: (store (s32))
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SI_RETURN
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...
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---
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name: combine_shl
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1, $vgpr31
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liveins: $vgpr0, $vgpr1
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; CHECK-LABEL: name: combine_shl
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; CHECK: liveins: $vgpr0, $vgpr1, $vgpr31, $vgpr0, $vgpr1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
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; CHECK-NEXT: [[MV:%[0-9]+]]:_(p0) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)
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; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
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; CHECK-NEXT: G_STORE [[C]](s32), [[MV]](p0) :: (store (s32))
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; CHECK-NEXT: SI_RETURN
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%0:_(s32) = COPY $vgpr0
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%1:_(s32) = COPY $vgpr1
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%2:_(p0) = G_MERGE_VALUES %0(s32), %1(s32)
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%3:_(s32) = G_CONSTANT i32 16
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%4:_(s32) = G_CONSTANT i32 4294901760
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%5:_(s32) = G_SHL %4, %3(s32)
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G_STORE %5(s32), %2(p0) :: (store (s32))
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SI_RETURN
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...
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---
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name: combine_ashr2
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1, $vgpr31
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liveins: $vgpr0, $vgpr1
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; CHECK-LABEL: name: combine_ashr2
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; CHECK: liveins: $vgpr0, $vgpr1, $vgpr31, $vgpr0, $vgpr1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
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; CHECK-NEXT: [[MV:%[0-9]+]]:_(p0) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)
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; CHECK-NEXT: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 -1
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; CHECK-NEXT: G_STORE [[C]](s8), [[MV]](p0) :: (store (s8))
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; CHECK-NEXT: SI_RETURN
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%0:_(s32) = COPY $vgpr0
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%1:_(s32) = COPY $vgpr1
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%2:_(p0) = G_MERGE_VALUES %0(s32), %1(s32)
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%3:_(s32) = G_CONSTANT i32 1
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%4:_(s8) = G_CONSTANT i8 -2
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%5:_(s8) = G_ASHR %4, %3(s32)
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G_STORE %5(s8), %2(p0) :: (store (s8))
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SI_RETURN
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...
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---
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name: combine_vector_lshr
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1, $vgpr31
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liveins: $vgpr0, $vgpr1
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; CHECK-LABEL: name: combine_vector_lshr
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; CHECK: liveins: $vgpr0, $vgpr1, $vgpr31, $vgpr0, $vgpr1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
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; CHECK-NEXT: $vgpr0 = COPY [[C]](s32)
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; CHECK-NEXT: $vgpr1 = COPY [[C]](s32)
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; CHECK-NEXT: SI_RETURN implicit $vgpr0, implicit $vgpr1
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%0:_(<2 x s32>) = G_IMPLICIT_DEF
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%1:_(s32) = G_CONSTANT i32 511
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%2:_(s32) = G_CONSTANT i32 0
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%3:_(s32) = G_CONSTANT i32 1
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%4:_(s32) = G_CONSTANT i32 9
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%5:_(<2 x s32>) = G_BUILD_VECTOR %4(s32), %4(s32)
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%6:_(<2 x s32>) = G_INSERT_VECTOR_ELT %0, %1(s32), %2(s32)
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%7:_(<2 x s32>) = G_INSERT_VECTOR_ELT %6, %1(s32), %3(s32)
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%8:_(<2 x s32>) = G_LSHR %7, %5(<2 x s32>)
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%9:_(s32), %10:_(s32) = G_UNMERGE_VALUES %8(<2 x s32>)
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$vgpr0 = COPY %9(s32)
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$vgpr1 = COPY %10(s32)
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SI_RETURN implicit $vgpr0, implicit $vgpr1
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...
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---
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name: combine_vector_shl
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1, $vgpr31
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liveins: $vgpr0, $vgpr1
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; CHECK-LABEL: name: combine_vector_shl
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; CHECK: liveins: $vgpr0, $vgpr1, $vgpr31, $vgpr0, $vgpr1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
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; CHECK-NEXT: $vgpr0 = COPY [[C]](s32)
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; CHECK-NEXT: $vgpr1 = COPY [[C]](s32)
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; CHECK-NEXT: SI_RETURN implicit $vgpr0, implicit $vgpr1
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%0:_(<2 x s32>) = G_IMPLICIT_DEF
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%1:_(s32) = G_CONSTANT i32 4294901760
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%2:_(s32) = G_CONSTANT i32 0
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%3:_(s32) = G_CONSTANT i32 1
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%4:_(s32) = G_CONSTANT i32 16
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%5:_(<2 x s32>) = G_BUILD_VECTOR %4(s32), %4(s32)
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%6:_(<2 x s32>) = G_INSERT_VECTOR_ELT %0, %1(s32), %2(s32)
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%7:_(<2 x s32>) = G_INSERT_VECTOR_ELT %6, %1(s32), %3(s32)
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%8:_(<2 x s32>) = G_SHL %7, %5(<2 x s32>)
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%9:_(s32), %10:_(s32) = G_UNMERGE_VALUES %8(<2 x s32>)
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$vgpr0 = COPY %9(s32)
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$vgpr1 = COPY %10(s32)
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SI_RETURN implicit $vgpr0, implicit $vgpr1
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...
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---
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name: combine_vector_ashr
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1, $vgpr31
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liveins: $vgpr0, $vgpr1
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; CHECK-LABEL: name: combine_vector_ashr
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; CHECK: liveins: $vgpr0, $vgpr1, $vgpr31, $vgpr0, $vgpr1
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
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; CHECK-NEXT: $vgpr0 = COPY [[C]](s32)
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; CHECK-NEXT: $vgpr1 = COPY [[C]](s32)
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; CHECK-NEXT: SI_RETURN implicit $vgpr0, implicit $vgpr1
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%0:_(<2 x s32>) = G_IMPLICIT_DEF
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%1:_(s32) = G_CONSTANT i32 -1
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%2:_(s32) = G_CONSTANT i32 0
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%3:_(s32) = G_CONSTANT i32 1
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%4:_(s32) = G_CONSTANT i32 1
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%5:_(<2 x s32>) = G_BUILD_VECTOR %4(s32), %4(s32)
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%6:_(<2 x s32>) = G_INSERT_VECTOR_ELT %0, %1(s32), %2(s32)
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%7:_(<2 x s32>) = G_INSERT_VECTOR_ELT %6, %1(s32), %3(s32)
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%8:_(<2 x s32>) = G_ASHR %7, %5(<2 x s32>)
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%9:_(s32), %10:_(s32) = G_UNMERGE_VALUES %8(<2 x s32>)
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$vgpr0 = COPY %9(s32)
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$vgpr1 = COPY %10(s32)
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SI_RETURN implicit $vgpr0, implicit $vgpr1
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...
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