derek/TheRock
1
0 Fork 0
Code Issues Pull Requests Actions 1 Packages Projects Releases Wiki Activity
Files
1a182e2dac58879f215c0fad0f5f78c76dcafe56
TheRock/compiler/amd-llvm/llvm/test/CodeGen/AMDGPU/GlobalISel/compute-num-sign-bits-med3.mir
T
derek.holloway 7502bf64a4
CodeQL / Analyze (actions) (push) Canceled after 0s
Details
CodeQL / Analyze (python) (push) Canceled after 0s
Details
pre-commit / pre-commit (push) Canceled after 0s
Details
Multi-Arch CI / setup (push) Canceled after 0s
Details
Publish build_manylinux_x86_64 images / publish_build_manylinux_x86_64 (push) Canceled after 0s
Details
Setup (Multi-Arch) / setup (push) Canceled after 0s
Details
Multi-Arch CI / Linux::${{ fromJSON(needs.setup.outputs.linux_build_config || '{}').build_variant_label || 'skip' }} (push) Canceled after 0s
Details
Publish TheRock Docker image / build-and-push-image (push) Canceled after 0s
Details
Publish no_rocm_image_ubi10 image / publish_no_rocm_image_ubi10 (push) Canceled after 0s
Details
Multi-Arch CI / Windows::${{ fromJSON(needs.setup.outputs.windows_build_config || '{}').build_variant_label || 'skip' }} (push) Canceled after 0s
Details
Publish TheRock Docker image / build-and-push-image (push) Canceled after 0s
Details
Multi-Arch CI / Manifest Diff (push) Canceled after 0s
Details
TheRock Manifest Diff Report / Generate Manifest Diff Report (push) Canceled after 0s
Details
Multi-Arch CI / CI Summary (push) Canceled after 0s
Details
Publish no_rocm_image_ubuntu24_04 images / publish_no_rocm_image_ubuntu24_04 (push) Canceled after 0s
Details
Publish no_rocm_image_ubuntu24_04_ocl_rt images / publish_no_rocm_image_ubuntu24_04_ocl_rt (push) Canceled after 0s
Details
Publish TheRock Docker image / build-and-push-image (push) Canceled after 0s
Details
Publish TheRock Docker image / build-and-push-image (push) Canceled after 0s
Details
Publish no_rocm_image_ubuntu24_04 images / publish_no_rocm_image_ubuntu24_04_rocgdb (push) Canceled after 0s
Details
Publish no_rocm_image_ubuntu24_04_rocgdb images / publish_no_rocm_image_ubuntu24_04_rocgdb (push) Canceled after 0s
Details
Publish no_rocm_image_ubuntu24_04 images / publish_no_rocm_image_ubuntu24_04_ocl_rt (push) Canceled after 0s
Details
Publish TheRock Docker image / build-and-push-image (push) Canceled after 0s
Details
Unit Tests / Unit Tests :: ubuntu-24.04 (push) Canceled after 0s
Details
Unit Tests / Unit Tests :: windows-2022 (push) Canceled after 0s
Details
Publish no_rocm_image_ubuntu24_04 images / publish_no_rocm_image_ubuntu24_04_media (push) Canceled after 0s
Details
Unit Tests / Unit Tests Summary (push) Canceled after 0s
Details
Publish no_rocm_image_ubuntu24_04 images / publish_no_rocm_image_ubuntu24_04_openmpi (push) Canceled after 0s
Details
Flatten subprojects into a single base monorepo
2026-09-02 16:34:47 -07:00

168 lines
5.4 KiB
YAML
Raw Blame History

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 2
# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -run-pass=amdgpu-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s
---
name: known_sign_bits_smed3_0
legalized: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $vgpr0
; CHECK-LABEL: name: known_sign_bits_smed3_0
; CHECK: liveins: $vgpr0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %val:_(s32) = COPY $vgpr0
; CHECK-NEXT: %val0:_(s32) = G_SEXT_INREG %val, 8
; CHECK-NEXT: %val1:_(s32) = G_CONSTANT i32 -255
; CHECK-NEXT: %val2:_(s32) = G_CONSTANT i32 255
; CHECK-NEXT: %smed3:_(s32) = G_AMDGPU_SMED3 %val0, %val1, %val2
; CHECK-NEXT: $vgpr0 = COPY %smed3(s32)
%val:_(s32) = COPY $vgpr0
%val0:_(s32) = G_SEXT_INREG %val, 8
%val1:_(s32) = G_CONSTANT i32 -255
%val2:_(s32) = G_CONSTANT i32 255
%smed3:_(s32) = G_AMDGPU_SMED3 %val0, %val1, %val2
%inreg:_(s32) = G_SEXT_INREG %smed3, 9
$vgpr0 = COPY %inreg
...
---
name: known_sign_bits_smed3_1
legalized: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $vgpr0
; CHECK-LABEL: name: known_sign_bits_smed3_1
; CHECK: liveins: $vgpr0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %val:_(s32) = COPY $vgpr0
; CHECK-NEXT: %val0:_(s32) = G_SEXT_INREG %val, 8
; CHECK-NEXT: %val1:_(s32) = G_CONSTANT i32 -255
; CHECK-NEXT: %val2:_(s32) = G_CONSTANT i32 255
; CHECK-NEXT: %smed3:_(s32) = G_AMDGPU_SMED3 %val1, %val0, %val2
; CHECK-NEXT: $vgpr0 = COPY %smed3(s32)
%val:_(s32) = COPY $vgpr0
%val0:_(s32) = G_SEXT_INREG %val, 8
%val1:_(s32) = G_CONSTANT i32 -255
%val2:_(s32) = G_CONSTANT i32 255
%smed3:_(s32) = G_AMDGPU_SMED3 %val1, %val0, %val2
%inreg:_(s32) = G_SEXT_INREG %smed3, 9
$vgpr0 = COPY %inreg
...
---
name: known_sign_bits_smed3_2
legalized: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $vgpr0
; CHECK-LABEL: name: known_sign_bits_smed3_2
; CHECK: liveins: $vgpr0
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %val:_(s32) = COPY $vgpr0
; CHECK-NEXT: %val0:_(s32) = G_SEXT_INREG %val, 8
; CHECK-NEXT: %val1:_(s32) = G_CONSTANT i32 -256
; CHECK-NEXT: %val2:_(s32) = G_CONSTANT i32 128
; CHECK-NEXT: %smed3:_(s32) = G_AMDGPU_SMED3 %val1, %val2, %val0
; CHECK-NEXT: $vgpr0 = COPY %smed3(s32)
%val:_(s32) = COPY $vgpr0
%val0:_(s32) = G_SEXT_INREG %val, 8
%val1:_(s32) = G_CONSTANT i32 -256
%val2:_(s32) = G_CONSTANT i32 128
%smed3:_(s32) = G_AMDGPU_SMED3 %val1, %val2, %val0
%inreg:_(s32) = G_SEXT_INREG %smed3, 9
$vgpr0 = COPY %inreg
...
---
name: not_enough_sign_bits_smed3_0
legalized: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $vgpr0, $vgpr1, $vgpr2
; CHECK-LABEL: name: not_enough_sign_bits_smed3_0
; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %val:_(s32) = COPY $vgpr0
; CHECK-NEXT: %val0:_(s32) = G_SEXT_INREG %val, 8
; CHECK-NEXT: %val1:_(s32) = G_SEXT_INREG %val, 9
; CHECK-NEXT: %val2:_(s32) = G_SEXT_INREG %val, 9
; CHECK-NEXT: %smed3:_(s32) = G_AMDGPU_SMED3 %val0, %val1, %val2
; CHECK-NEXT: %inreg:_(s32) = G_SEXT_INREG %smed3, 8
; CHECK-NEXT: $vgpr0 = COPY %inreg(s32)
%val:_(s32) = COPY $vgpr0
%val0:_(s32) = G_SEXT_INREG %val, 8
%val1:_(s32) = G_SEXT_INREG %val, 9
%val2:_(s32) = G_SEXT_INREG %val, 9
%smed3:_(s32) = G_AMDGPU_SMED3 %val0, %val1, %val2
%inreg:_(s32) = G_SEXT_INREG %smed3, 8
$vgpr0 = COPY %inreg
...
---
name: not_enough_sign_bits_smed3_1
legalized: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $vgpr0, $vgpr1, $vgpr2
; CHECK-LABEL: name: not_enough_sign_bits_smed3_1
; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %val:_(s32) = COPY $vgpr0
; CHECK-NEXT: %val0:_(s32) = G_SEXT_INREG %val, 9
; CHECK-NEXT: %val1:_(s32) = G_SEXT_INREG %val, 8
; CHECK-NEXT: %val2:_(s32) = G_SEXT_INREG %val, 9
; CHECK-NEXT: %smed3:_(s32) = G_AMDGPU_SMED3 %val0, %val1, %val2
; CHECK-NEXT: %inreg:_(s32) = G_SEXT_INREG %smed3, 8
; CHECK-NEXT: $vgpr0 = COPY %inreg(s32)
%val:_(s32) = COPY $vgpr0
%val0:_(s32) = G_SEXT_INREG %val, 9
%val1:_(s32) = G_SEXT_INREG %val, 8
%val2:_(s32) = G_SEXT_INREG %val, 9
%smed3:_(s32) = G_AMDGPU_SMED3 %val0, %val1, %val2
%inreg:_(s32) = G_SEXT_INREG %smed3, 8
$vgpr0 = COPY %inreg
...
---
name: not_enough_sign_bits_smed3_2
legalized: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $vgpr0, $vgpr1, $vgpr2
; CHECK-LABEL: name: not_enough_sign_bits_smed3_2
; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: %val:_(s32) = COPY $vgpr0
; CHECK-NEXT: %val0:_(s32) = G_SEXT_INREG %val, 8
; CHECK-NEXT: %val1:_(s32) = G_SEXT_INREG %val, 8
; CHECK-NEXT: %val2:_(s32) = G_SEXT_INREG %val, 9
; CHECK-NEXT: %smed3:_(s32) = G_AMDGPU_SMED3 %val0, %val1, %val2
; CHECK-NEXT: %inreg:_(s32) = G_SEXT_INREG %smed3, 8
; CHECK-NEXT: $vgpr0 = COPY %inreg(s32)
%val:_(s32) = COPY $vgpr0
%val0:_(s32) = G_SEXT_INREG %val, 8
%val1:_(s32) = G_SEXT_INREG %val, 8
%val2:_(s32) = G_SEXT_INREG %val, 9
%smed3:_(s32) = G_AMDGPU_SMED3 %val0, %val1, %val2
%inreg:_(s32) = G_SEXT_INREG %smed3, 8
$vgpr0 = COPY %inreg
...
Reference in new issue View Git Blame Copy Permalink