derek.holloway
7502bf64a4
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628 lines
27 KiB
YAML
628 lines
27 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4
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# RUN: llc -mtriple=amdgcn-mesa-amdpal -mcpu=gfx1010 -run-pass=amdgpu-global-isel-divergence-lowering -verify-machineinstrs %s -o - | FileCheck -check-prefix=GFX10 %s
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--- |
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define void @divergent_i1_phi_uniform_branch() {ret void}
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define void @divergent_i1_phi_uniform_branch_simple() {ret void}
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define void @divergent_i1_phi_used_inside_loop() {ret void}
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define void @divergent_i1_phi_used_inside_loop_bigger_loop_body() {ret void}
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define void @single_lane_execution_attribute() #0 {ret void}
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attributes #0 = {"amdgpu-flat-work-group-size"="1,1"}
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...
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---
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name: divergent_i1_phi_uniform_branch
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legalized: true
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tracksRegLiveness: true
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body: |
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; GFX10-LABEL: name: divergent_i1_phi_uniform_branch
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; GFX10: bb.0:
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; GFX10-NEXT: successors: %bb.1(0x30000000), %bb.2(0x50000000)
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; GFX10-NEXT: liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4
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; GFX10-NEXT: {{ $}}
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; GFX10-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
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; GFX10-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
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; GFX10-NEXT: [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)
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; GFX10-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
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; GFX10-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr0
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; GFX10-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $vgpr3
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; GFX10-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $vgpr4
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; GFX10-NEXT: [[MV1:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY4]](s32), [[COPY5]](s32)
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; GFX10-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 6
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; GFX10-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[COPY2]](s32), [[C]]
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; GFX10-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
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; GFX10-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY3]](s32), [[C1]]
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; GFX10-NEXT: [[COPY6:%[0-9]+]]:sreg_32(s1) = COPY [[ICMP]](s1)
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; GFX10-NEXT: G_BRCOND [[ICMP1]](s1), %bb.2
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; GFX10-NEXT: G_BR %bb.1
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; GFX10-NEXT: {{ $}}
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; GFX10-NEXT: bb.1:
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; GFX10-NEXT: successors: %bb.3(0x80000000)
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; GFX10-NEXT: {{ $}}
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; GFX10-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 123
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; GFX10-NEXT: G_STORE [[C2]](s32), [[MV1]](p1) :: (store (s32), addrspace 1)
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; GFX10-NEXT: G_BR %bb.3
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; GFX10-NEXT: {{ $}}
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; GFX10-NEXT: bb.2:
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; GFX10-NEXT: successors: %bb.4(0x80000000)
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; GFX10-NEXT: {{ $}}
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; GFX10-NEXT: [[PHI:%[0-9]+]]:sreg_32(s1) = PHI [[COPY6]](s1), %bb.0, %20(s1), %bb.3
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; GFX10-NEXT: [[COPY7:%[0-9]+]]:sreg_32(s1) = COPY [[PHI]](s1)
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; GFX10-NEXT: G_BR %bb.4
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; GFX10-NEXT: {{ $}}
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; GFX10-NEXT: bb.3:
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; GFX10-NEXT: successors: %bb.2(0x80000000)
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; GFX10-NEXT: {{ $}}
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; GFX10-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
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; GFX10-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[COPY2]](s32), [[C3]]
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; GFX10-NEXT: [[COPY8:%[0-9]+]]:sreg_32(s1) = COPY [[ICMP2]](s1)
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; GFX10-NEXT: G_BR %bb.2
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; GFX10-NEXT: {{ $}}
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; GFX10-NEXT: bb.4:
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; GFX10-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[COPY7]](s1)
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; GFX10-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
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; GFX10-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[SEXT]], [[C4]]
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; GFX10-NEXT: G_STORE [[ADD]](s32), [[MV]](p1) :: (store (s32), addrspace 1)
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; GFX10-NEXT: S_ENDPGM 0
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bb.0:
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successors: %bb.1(0x30000000), %bb.2(0x50000000)
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liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4
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%0:_(s32) = COPY $vgpr0
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%1:_(s32) = COPY $vgpr1
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%2:_(p1) = G_MERGE_VALUES %0(s32), %1(s32)
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%3:_(s32) = COPY $vgpr2
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%4:_(s32) = COPY $sgpr0
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%5:_(s32) = COPY $vgpr3
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%6:_(s32) = COPY $vgpr4
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%7:_(p1) = G_MERGE_VALUES %5(s32), %6(s32)
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%8:_(s32) = G_CONSTANT i32 6
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%9:_(s1) = G_ICMP intpred(uge), %3(s32), %8
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%10:_(s32) = G_CONSTANT i32 0
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%11:_(s1) = G_ICMP intpred(ne), %4(s32), %10
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G_BRCOND %11(s1), %bb.2
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G_BR %bb.1
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bb.1:
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successors: %bb.3(0x80000000)
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%12:_(s32) = G_CONSTANT i32 123
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G_STORE %12(s32), %7(p1) :: (store (s32), addrspace 1)
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G_BR %bb.3
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bb.2:
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successors: %bb.4(0x80000000)
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%13:_(s1) = G_PHI %14(s1), %bb.3, %9(s1), %bb.0
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G_BR %bb.4
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bb.3:
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successors: %bb.2(0x80000000)
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%15:_(s32) = G_CONSTANT i32 1
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%14:_(s1) = G_ICMP intpred(ult), %3(s32), %15
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G_BR %bb.2
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bb.4:
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%16:_(s32) = G_SEXT %13(s1)
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%17:_(s32) = G_CONSTANT i32 2
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%18:_(s32) = G_ADD %16, %17
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G_STORE %18(s32), %2(p1) :: (store (s32), addrspace 1)
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S_ENDPGM 0
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...
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---
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name: divergent_i1_phi_uniform_branch_simple
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legalized: true
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tracksRegLiveness: true
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body: |
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; GFX10-LABEL: name: divergent_i1_phi_uniform_branch_simple
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; GFX10: bb.0:
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; GFX10-NEXT: successors: %bb.1(0x30000000), %bb.2(0x50000000)
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; GFX10-NEXT: liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr2
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; GFX10-NEXT: {{ $}}
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; GFX10-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
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; GFX10-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
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; GFX10-NEXT: [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)
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; GFX10-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
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; GFX10-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $sgpr0
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; GFX10-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 6
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; GFX10-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(uge), [[COPY2]](s32), [[C]]
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; GFX10-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
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; GFX10-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY3]](s32), [[C1]]
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; GFX10-NEXT: [[COPY4:%[0-9]+]]:sreg_32(s1) = COPY [[ICMP]](s1)
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; GFX10-NEXT: [[COPY5:%[0-9]+]]:sreg_32(s1) = COPY [[COPY4]](s1)
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; GFX10-NEXT: G_BRCOND [[ICMP1]](s1), %bb.2
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; GFX10-NEXT: G_BR %bb.1
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; GFX10-NEXT: {{ $}}
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; GFX10-NEXT: bb.1:
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; GFX10-NEXT: successors: %bb.2(0x80000000)
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; GFX10-NEXT: {{ $}}
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; GFX10-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
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; GFX10-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[COPY2]](s32), [[C2]]
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; GFX10-NEXT: [[COPY6:%[0-9]+]]:sreg_32(s1) = COPY [[ICMP2]](s1)
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; GFX10-NEXT: [[S_ANDN2_B32_:%[0-9]+]]:sreg_32(s1) = S_ANDN2_B32 [[COPY5]](s1), $exec_lo, implicit-def $scc
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; GFX10-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32(s1) = S_AND_B32 $exec_lo, [[COPY6]](s1), implicit-def $scc
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; GFX10-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32(s1) = S_OR_B32 [[S_ANDN2_B32_]](s1), [[S_AND_B32_]](s1), implicit-def $scc
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; GFX10-NEXT: {{ $}}
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; GFX10-NEXT: bb.2:
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; GFX10-NEXT: [[PHI:%[0-9]+]]:sreg_32(s1) = PHI [[COPY4]](s1), %bb.0, [[S_OR_B32_]](s1), %bb.1
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; GFX10-NEXT: [[COPY7:%[0-9]+]]:sreg_32(s1) = COPY [[PHI]](s1)
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; GFX10-NEXT: [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[COPY7]](s1)
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; GFX10-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
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; GFX10-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[SEXT]], [[C3]]
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; GFX10-NEXT: G_STORE [[ADD]](s32), [[MV]](p1) :: (store (s32), addrspace 1)
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; GFX10-NEXT: S_ENDPGM 0
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bb.0:
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successors: %bb.1(0x30000000), %bb.2(0x50000000)
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liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr2
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%0:_(s32) = COPY $vgpr0
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%1:_(s32) = COPY $vgpr1
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%2:_(p1) = G_MERGE_VALUES %0(s32), %1(s32)
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%3:_(s32) = COPY $vgpr2
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%4:_(s32) = COPY $sgpr0
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%5:_(s32) = G_CONSTANT i32 6
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%6:_(s1) = G_ICMP intpred(uge), %3(s32), %5
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%7:_(s32) = G_CONSTANT i32 0
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%8:_(s1) = G_ICMP intpred(ne), %4(s32), %7
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G_BRCOND %8(s1), %bb.2
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G_BR %bb.1
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bb.1:
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successors: %bb.2(0x80000000)
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%9:_(s32) = G_CONSTANT i32 1
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%10:_(s1) = G_ICMP intpred(ult), %3(s32), %9
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bb.2:
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%11:_(s1) = G_PHI %6(s1), %bb.0, %10(s1), %bb.1
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%12:_(s32) = G_SEXT %11(s1)
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%13:_(s32) = G_CONSTANT i32 2
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%14:_(s32) = G_ADD %12, %13
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G_STORE %14(s32), %2(p1) :: (store (s32), addrspace 1)
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S_ENDPGM 0
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...
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---
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name: divergent_i1_phi_used_inside_loop
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legalized: true
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tracksRegLiveness: true
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body: |
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; GFX10-LABEL: name: divergent_i1_phi_used_inside_loop
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; GFX10: bb.0:
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; GFX10-NEXT: successors: %bb.1(0x80000000)
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; GFX10-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2
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; GFX10-NEXT: {{ $}}
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; GFX10-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
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; GFX10-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
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; GFX10-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
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; GFX10-NEXT: [[MV:%[0-9]+]]:_(p0) = G_MERGE_VALUES [[COPY1]](s32), [[COPY2]](s32)
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; GFX10-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
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; GFX10-NEXT: [[C1:%[0-9]+]]:_(s1) = G_CONSTANT i1 true
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; GFX10-NEXT: [[DEF:%[0-9]+]]:sreg_32(s1) = IMPLICIT_DEF
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; GFX10-NEXT: {{ $}}
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; GFX10-NEXT: bb.1:
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; GFX10-NEXT: successors: %bb.2(0x04000000), %bb.1(0x7c000000)
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; GFX10-NEXT: {{ $}}
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; GFX10-NEXT: [[PHI:%[0-9]+]]:sreg_32(s1) = PHI [[DEF]](s1), %bb.0, %19(s1), %bb.1
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; GFX10-NEXT: [[PHI1:%[0-9]+]]:_(s32) = G_PHI %7(s32), %bb.1, [[C]](s32), %bb.0
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; GFX10-NEXT: [[PHI2:%[0-9]+]]:_(s32) = G_PHI [[C]](s32), %bb.0, %9(s32), %bb.1
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; GFX10-NEXT: [[PHI3:%[0-9]+]]:_(s1) = G_PHI [[C1]](s1), %bb.0, %11(s1), %bb.1
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; GFX10-NEXT: [[COPY3:%[0-9]+]]:sreg_32(s1) = COPY [[PHI]](s1)
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; GFX10-NEXT: [[C2:%[0-9]+]]:_(s1) = G_CONSTANT i1 true
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; GFX10-NEXT: [[XOR:%[0-9]+]]:_(s1) = G_XOR [[PHI3]], [[C2]]
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; GFX10-NEXT: [[COPY4:%[0-9]+]]:sreg_32(s1) = COPY [[XOR]](s1)
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; GFX10-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[PHI2]](s32)
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; GFX10-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[UITOFP]](s32), [[COPY]]
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; GFX10-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
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; GFX10-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[PHI2]], [[C3]]
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; GFX10-NEXT: [[INT:%[0-9]+]]:sreg_32_xm0_xexec(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.if.break), [[FCMP]](s1), [[PHI1]](s32)
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; GFX10-NEXT: [[S_ANDN2_B32_:%[0-9]+]]:sreg_32(s1) = S_ANDN2_B32 [[COPY3]](s1), $exec_lo, implicit-def $scc
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; GFX10-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32(s1) = S_AND_B32 $exec_lo, [[COPY4]](s1), implicit-def $scc
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; GFX10-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32(s1) = S_OR_B32 [[S_ANDN2_B32_]](s1), [[S_AND_B32_]](s1), implicit-def $scc
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; GFX10-NEXT: SI_LOOP [[INT]](s32), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec
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; GFX10-NEXT: G_BR %bb.2
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; GFX10-NEXT: {{ $}}
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; GFX10-NEXT: bb.2:
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; GFX10-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[INT]](s32)
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; GFX10-NEXT: [[C4:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
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; GFX10-NEXT: [[C5:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00
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; GFX10-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[S_OR_B32_]](s1), [[C5]], [[C4]]
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; GFX10-NEXT: G_STORE [[SELECT]](s32), [[MV]](p0) :: (store (s32))
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; GFX10-NEXT: SI_RETURN
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bb.0:
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successors: %bb.1(0x80000000)
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liveins: $vgpr0, $vgpr1, $vgpr2
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%0:_(s32) = COPY $vgpr0
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%1:_(s32) = COPY $vgpr1
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%2:_(s32) = COPY $vgpr2
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%3:_(p0) = G_MERGE_VALUES %1(s32), %2(s32)
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%4:_(s32) = G_CONSTANT i32 0
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%5:_(s1) = G_CONSTANT i1 true
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bb.1:
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successors: %bb.2(0x04000000), %bb.1(0x7c000000)
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%6:_(s32) = G_PHI %7(s32), %bb.1, %4(s32), %bb.0
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%8:_(s32) = G_PHI %4(s32), %bb.0, %9(s32), %bb.1
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%10:_(s1) = G_PHI %5(s1), %bb.0, %11(s1), %bb.1
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%12:_(s1) = G_CONSTANT i1 true
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%11:_(s1) = G_XOR %10, %12
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|
%13:_(s32) = G_UITOFP %8(s32)
|
|
%14:_(s1) = G_FCMP floatpred(ogt), %13(s32), %0
|
|
%15:_(s32) = G_CONSTANT i32 1
|
|
%9:_(s32) = G_ADD %8, %15
|
|
%7:sreg_32_xm0_xexec(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.if.break), %14(s1), %6(s32)
|
|
SI_LOOP %7(s32), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec
|
|
G_BR %bb.2
|
|
|
|
bb.2:
|
|
G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %7(s32)
|
|
%16:_(s32) = G_FCONSTANT float 0.000000e+00
|
|
%17:_(s32) = G_FCONSTANT float 1.000000e+00
|
|
%18:_(s32) = G_SELECT %11(s1), %17, %16
|
|
G_STORE %18(s32), %3(p0) :: (store (s32))
|
|
SI_RETURN
|
|
...
|
|
|
|
---
|
|
name: divergent_i1_phi_used_inside_loop_bigger_loop_body
|
|
legalized: true
|
|
tracksRegLiveness: true
|
|
body: |
|
|
; GFX10-LABEL: name: divergent_i1_phi_used_inside_loop_bigger_loop_body
|
|
; GFX10: bb.0:
|
|
; GFX10-NEXT: successors: %bb.1(0x80000000)
|
|
; GFX10-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7
|
|
; GFX10-NEXT: {{ $}}
|
|
; GFX10-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
|
|
; GFX10-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
|
|
; GFX10-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
|
|
; GFX10-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3
|
|
; GFX10-NEXT: [[MV:%[0-9]+]]:_(p0) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32)
|
|
; GFX10-NEXT: [[COPY4:%[0-9]+]]:_(s32) = COPY $vgpr4
|
|
; GFX10-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY $vgpr5
|
|
; GFX10-NEXT: [[MV1:%[0-9]+]]:_(p0) = G_MERGE_VALUES [[COPY4]](s32), [[COPY5]](s32)
|
|
; GFX10-NEXT: [[COPY6:%[0-9]+]]:_(s32) = COPY $vgpr6
|
|
; GFX10-NEXT: [[COPY7:%[0-9]+]]:_(s32) = COPY $vgpr7
|
|
; GFX10-NEXT: [[MV2:%[0-9]+]]:_(p0) = G_MERGE_VALUES [[COPY6]](s32), [[COPY7]](s32)
|
|
; GFX10-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00
|
|
; GFX10-NEXT: [[FCMP:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[COPY1]](s32), [[C]]
|
|
; GFX10-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
|
|
; GFX10-NEXT: [[DEF:%[0-9]+]]:sreg_32(s1) = IMPLICIT_DEF
|
|
; GFX10-NEXT: [[COPY8:%[0-9]+]]:sreg_32(s1) = COPY [[FCMP]](s1)
|
|
; GFX10-NEXT: {{ $}}
|
|
; GFX10-NEXT: bb.1:
|
|
; GFX10-NEXT: successors: %bb.4(0x40000000), %bb.2(0x40000000)
|
|
; GFX10-NEXT: {{ $}}
|
|
; GFX10-NEXT: [[PHI:%[0-9]+]]:sreg_32(s1) = PHI [[COPY8]](s1), %bb.0, %44(s1), %bb.5
|
|
; GFX10-NEXT: [[PHI1:%[0-9]+]]:sreg_32(s1) = PHI [[DEF]](s1), %bb.0, %36(s1), %bb.5
|
|
; GFX10-NEXT: [[PHI2:%[0-9]+]]:_(s32) = G_PHI %15(s32), %bb.5, [[C1]](s32), %bb.0
|
|
; GFX10-NEXT: [[PHI3:%[0-9]+]]:_(s32) = G_PHI [[C1]](s32), %bb.0, %17(s32), %bb.5
|
|
; GFX10-NEXT: [[COPY9:%[0-9]+]]:sreg_32(s1) = COPY [[PHI]](s1)
|
|
; GFX10-NEXT: [[COPY10:%[0-9]+]]:sreg_32(s1) = COPY [[PHI1]](s1)
|
|
; GFX10-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1000
|
|
; GFX10-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(sle), [[PHI3]](s32), [[C2]]
|
|
; GFX10-NEXT: [[C3:%[0-9]+]]:_(s1) = G_CONSTANT i1 true
|
|
; GFX10-NEXT: G_BRCOND [[ICMP]](s1), %bb.4
|
|
; GFX10-NEXT: G_BR %bb.2
|
|
; GFX10-NEXT: {{ $}}
|
|
; GFX10-NEXT: bb.2:
|
|
; GFX10-NEXT: successors: %bb.3(0x40000000), %bb.5(0x40000000)
|
|
; GFX10-NEXT: {{ $}}
|
|
; GFX10-NEXT: [[PHI4:%[0-9]+]]:_(s1) = G_PHI %24(s1), %bb.4, [[C3]](s1), %bb.1
|
|
; GFX10-NEXT: [[C4:%[0-9]+]]:_(s1) = G_CONSTANT i1 true
|
|
; GFX10-NEXT: [[XOR:%[0-9]+]]:_(s1) = G_XOR [[PHI4]], [[C4]]
|
|
; GFX10-NEXT: G_BRCOND [[XOR]](s1), %bb.5
|
|
; GFX10-NEXT: G_BR %bb.3
|
|
; GFX10-NEXT: {{ $}}
|
|
; GFX10-NEXT: bb.3:
|
|
; GFX10-NEXT: successors: %bb.5(0x80000000)
|
|
; GFX10-NEXT: {{ $}}
|
|
; GFX10-NEXT: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 1000
|
|
; GFX10-NEXT: G_STORE [[C5]](s32), [[MV1]](p0) :: (store (s32))
|
|
; GFX10-NEXT: G_BR %bb.5
|
|
; GFX10-NEXT: {{ $}}
|
|
; GFX10-NEXT: bb.4:
|
|
; GFX10-NEXT: successors: %bb.2(0x80000000)
|
|
; GFX10-NEXT: {{ $}}
|
|
; GFX10-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 1000
|
|
; GFX10-NEXT: G_STORE [[C6]](s32), [[MV2]](p0) :: (store (s32))
|
|
; GFX10-NEXT: [[C7:%[0-9]+]]:_(s1) = G_CONSTANT i1 false
|
|
; GFX10-NEXT: G_BR %bb.2
|
|
; GFX10-NEXT: {{ $}}
|
|
; GFX10-NEXT: bb.5:
|
|
; GFX10-NEXT: successors: %bb.6(0x04000000), %bb.1(0x7c000000)
|
|
; GFX10-NEXT: {{ $}}
|
|
; GFX10-NEXT: [[C8:%[0-9]+]]:_(s1) = G_CONSTANT i1 true
|
|
; GFX10-NEXT: [[XOR1:%[0-9]+]]:_(s1) = G_XOR [[COPY9]], [[C8]]
|
|
; GFX10-NEXT: [[COPY11:%[0-9]+]]:sreg_32(s1) = COPY [[XOR1]](s1)
|
|
; GFX10-NEXT: [[UITOFP:%[0-9]+]]:_(s32) = G_UITOFP [[PHI3]](s32)
|
|
; GFX10-NEXT: [[FCMP1:%[0-9]+]]:_(s1) = G_FCMP floatpred(ogt), [[UITOFP]](s32), [[COPY]]
|
|
; GFX10-NEXT: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
|
|
; GFX10-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[PHI3]], [[C9]]
|
|
; GFX10-NEXT: [[INT:%[0-9]+]]:sreg_32_xm0_xexec(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.if.break), [[FCMP1]](s1), [[PHI2]](s32)
|
|
; GFX10-NEXT: [[S_ANDN2_B32_:%[0-9]+]]:sreg_32(s1) = S_ANDN2_B32 [[COPY10]](s1), $exec_lo, implicit-def $scc
|
|
; GFX10-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32(s1) = S_AND_B32 $exec_lo, [[COPY11]](s1), implicit-def $scc
|
|
; GFX10-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32(s1) = S_OR_B32 [[S_ANDN2_B32_]](s1), [[S_AND_B32_]](s1), implicit-def $scc
|
|
; GFX10-NEXT: [[COPY12:%[0-9]+]]:sreg_32(s1) = COPY [[XOR1]](s1)
|
|
; GFX10-NEXT: SI_LOOP [[INT]](s32), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec
|
|
; GFX10-NEXT: G_BR %bb.6
|
|
; GFX10-NEXT: {{ $}}
|
|
; GFX10-NEXT: bb.6:
|
|
; GFX10-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[INT]](s32)
|
|
; GFX10-NEXT: [[C10:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
|
|
; GFX10-NEXT: [[C11:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00
|
|
; GFX10-NEXT: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[S_OR_B32_]](s1), [[C11]], [[C10]]
|
|
; GFX10-NEXT: G_STORE [[SELECT]](s32), [[MV]](p0) :: (store (s32))
|
|
; GFX10-NEXT: SI_RETURN
|
|
bb.0:
|
|
successors: %bb.1(0x80000000)
|
|
liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7
|
|
|
|
%0:_(s32) = COPY $vgpr0
|
|
%1:_(s32) = COPY $vgpr1
|
|
%2:_(s32) = COPY $vgpr2
|
|
%3:_(s32) = COPY $vgpr3
|
|
%4:_(p0) = G_MERGE_VALUES %2(s32), %3(s32)
|
|
%5:_(s32) = COPY $vgpr4
|
|
%6:_(s32) = COPY $vgpr5
|
|
%7:_(p0) = G_MERGE_VALUES %5(s32), %6(s32)
|
|
%8:_(s32) = COPY $vgpr6
|
|
%9:_(s32) = COPY $vgpr7
|
|
%10:_(p0) = G_MERGE_VALUES %8(s32), %9(s32)
|
|
%11:_(s32) = G_FCONSTANT float 1.000000e+00
|
|
%12:_(s1) = G_FCMP floatpred(ogt), %1(s32), %11
|
|
%13:_(s32) = G_CONSTANT i32 0
|
|
|
|
bb.1:
|
|
successors: %bb.4(0x40000000), %bb.2(0x40000000)
|
|
|
|
%14:_(s32) = G_PHI %15(s32), %bb.5, %13(s32), %bb.0
|
|
%16:_(s32) = G_PHI %13(s32), %bb.0, %17(s32), %bb.5
|
|
%18:_(s1) = G_PHI %12(s1), %bb.0, %19(s1), %bb.5
|
|
%20:_(s32) = G_CONSTANT i32 1000
|
|
%21:_(s1) = G_ICMP intpred(sle), %16(s32), %20
|
|
%22:_(s1) = G_CONSTANT i1 true
|
|
G_BRCOND %21(s1), %bb.4
|
|
G_BR %bb.2
|
|
|
|
bb.2:
|
|
successors: %bb.3(0x40000000), %bb.5(0x40000000)
|
|
|
|
%23:_(s1) = G_PHI %24(s1), %bb.4, %22(s1), %bb.1
|
|
%25:_(s1) = G_CONSTANT i1 true
|
|
%26:_(s1) = G_XOR %23, %25
|
|
G_BRCOND %26(s1), %bb.5
|
|
G_BR %bb.3
|
|
|
|
bb.3:
|
|
successors: %bb.5(0x80000000)
|
|
|
|
%27:_(s32) = G_CONSTANT i32 1000
|
|
G_STORE %27(s32), %7(p0) :: (store (s32))
|
|
G_BR %bb.5
|
|
|
|
bb.4:
|
|
successors: %bb.2(0x80000000)
|
|
|
|
%28:_(s32) = G_CONSTANT i32 1000
|
|
G_STORE %28(s32), %10(p0) :: (store (s32))
|
|
%24:_(s1) = G_CONSTANT i1 false
|
|
G_BR %bb.2
|
|
|
|
bb.5:
|
|
successors: %bb.6(0x04000000), %bb.1(0x7c000000)
|
|
|
|
%29:_(s1) = G_CONSTANT i1 true
|
|
%19:_(s1) = G_XOR %18, %29
|
|
%30:_(s32) = G_UITOFP %16(s32)
|
|
%31:_(s1) = G_FCMP floatpred(ogt), %30(s32), %0
|
|
%32:_(s32) = G_CONSTANT i32 1
|
|
%17:_(s32) = G_ADD %16, %32
|
|
%15:sreg_32_xm0_xexec(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.if.break), %31(s1), %14(s32)
|
|
SI_LOOP %15(s32), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec
|
|
G_BR %bb.6
|
|
|
|
bb.6:
|
|
G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %15(s32)
|
|
%33:_(s32) = G_FCONSTANT float 0.000000e+00
|
|
%34:_(s32) = G_FCONSTANT float 1.000000e+00
|
|
%35:_(s32) = G_SELECT %19(s1), %34, %33
|
|
G_STORE %35(s32), %4(p0) :: (store (s32))
|
|
SI_RETURN
|
|
...
|
|
|
|
---
|
|
name: single_lane_execution_attribute
|
|
legalized: true
|
|
tracksRegLiveness: true
|
|
body: |
|
|
; GFX10-LABEL: name: single_lane_execution_attribute
|
|
; GFX10: bb.0:
|
|
; GFX10-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)
|
|
; GFX10-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0, $vgpr1, $vgpr2
|
|
; GFX10-NEXT: {{ $}}
|
|
; GFX10-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $sgpr0
|
|
; GFX10-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr1
|
|
; GFX10-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr0
|
|
; GFX10-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
|
|
; GFX10-NEXT: [[INT:%[0-9]+]]:_(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.s.getpc)
|
|
; GFX10-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -4294967296
|
|
; GFX10-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[INT]], [[C]]
|
|
; GFX10-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[COPY]](s32)
|
|
; GFX10-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[AND]], [[ZEXT]]
|
|
; GFX10-NEXT: [[INTTOPTR:%[0-9]+]]:_(p4) = G_INTTOPTR [[OR]](s64)
|
|
; GFX10-NEXT: [[LOAD:%[0-9]+]]:_(<8 x s32>) = G_LOAD [[INTTOPTR]](p4) :: (invariant load (<8 x s32>), align 16, addrspace 4)
|
|
; GFX10-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
|
|
; GFX10-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
|
|
; GFX10-NEXT: [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
|
|
; GFX10-NEXT: [[UV:%[0-9]+]]:_(<4 x s32>), [[UV1:%[0-9]+]]:_(<4 x s32>) = G_UNMERGE_VALUES [[LOAD]](<8 x s32>)
|
|
; GFX10-NEXT: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
|
|
; GFX10-NEXT: [[INT1:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.mbcnt.lo), [[C4]](s32), [[C1]](s32)
|
|
; GFX10-NEXT: [[INT2:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.mbcnt.hi), [[C4]](s32), [[INT1]](s32)
|
|
; GFX10-NEXT: [[FREEZE:%[0-9]+]]:_(s32) = G_FREEZE [[INT2]]
|
|
; GFX10-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[FREEZE]], [[C3]](s32)
|
|
; GFX10-NEXT: [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:_(s32) = G_AMDGPU_BUFFER_LOAD [[UV]](<4 x s32>), [[C1]](s32), [[SHL]], [[C1]], 0, 0, 0 :: (dereferenceable load (s32), align 1, addrspace 8)
|
|
; GFX10-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[AMDGPU_BUFFER_LOAD]](s32), [[C1]]
|
|
; GFX10-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[FREEZE]], [[C2]]
|
|
; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[AND1]](s32)
|
|
; GFX10-NEXT: [[C5:%[0-9]+]]:_(s1) = G_CONSTANT i1 true
|
|
; GFX10-NEXT: [[XOR:%[0-9]+]]:_(s1) = G_XOR [[TRUNC]], [[C5]]
|
|
; GFX10-NEXT: [[COPY3:%[0-9]+]]:sreg_32(s1) = COPY [[C5]](s1)
|
|
; GFX10-NEXT: G_BRCOND [[XOR]](s1), %bb.2
|
|
; GFX10-NEXT: G_BR %bb.1
|
|
; GFX10-NEXT: {{ $}}
|
|
; GFX10-NEXT: bb.1:
|
|
; GFX10-NEXT: successors: %bb.3(0x80000000)
|
|
; GFX10-NEXT: {{ $}}
|
|
; GFX10-NEXT: [[C6:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
|
|
; GFX10-NEXT: G_BR %bb.3
|
|
; GFX10-NEXT: {{ $}}
|
|
; GFX10-NEXT: bb.2:
|
|
; GFX10-NEXT: successors: %bb.5(0x40000000), %bb.6(0x40000000)
|
|
; GFX10-NEXT: {{ $}}
|
|
; GFX10-NEXT: [[PHI:%[0-9]+]]:sreg_32(s1) = PHI [[COPY3]](s1), %bb.0, %57(s1), %bb.4
|
|
; GFX10-NEXT: [[PHI1:%[0-9]+]]:_(s32) = G_PHI %29(s32), %bb.4, [[DEF]](s32), %bb.0
|
|
; GFX10-NEXT: [[COPY4:%[0-9]+]]:sreg_32(s1) = COPY [[PHI]](s1)
|
|
; GFX10-NEXT: G_BRCOND [[COPY4]](s1), %bb.5
|
|
; GFX10-NEXT: G_BR %bb.6
|
|
; GFX10-NEXT: {{ $}}
|
|
; GFX10-NEXT: bb.3:
|
|
; GFX10-NEXT: successors: %bb.4(0x04000000), %bb.3(0x7c000000)
|
|
; GFX10-NEXT: {{ $}}
|
|
; GFX10-NEXT: [[PHI2:%[0-9]+]]:_(s32) = G_PHI %33(s32), %bb.3, [[C6]](s32), %bb.1
|
|
; GFX10-NEXT: [[PHI3:%[0-9]+]]:_(s32) = G_PHI %35(s32), %bb.3, [[FREEZE]](s32), %bb.1
|
|
; GFX10-NEXT: [[PHI4:%[0-9]+]]:_(s32) = G_PHI %37(s32), %bb.3, [[C6]](s32), %bb.1
|
|
; GFX10-NEXT: [[C7:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
|
|
; GFX10-NEXT: [[AMDGPU_BUFFER_LOAD1:%[0-9]+]]:_(s32) = G_AMDGPU_BUFFER_LOAD [[UV]](<4 x s32>), [[C7]](s32), [[PHI2]], [[C7]], 0, 0, 0 :: (dereferenceable load (s32), align 1, addrspace 8)
|
|
; GFX10-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[AMDGPU_BUFFER_LOAD1]], [[PHI4]]
|
|
; GFX10-NEXT: [[COPY5:%[0-9]+]]:_(s32) = COPY [[ADD]](s32), implicit $exec_lo
|
|
; GFX10-NEXT: [[C8:%[0-9]+]]:_(s32) = G_CONSTANT i32 -1
|
|
; GFX10-NEXT: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[PHI3]], [[C8]]
|
|
; GFX10-NEXT: [[C9:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
|
|
; GFX10-NEXT: [[ADD2:%[0-9]+]]:_(s32) = G_ADD [[PHI2]], [[C9]]
|
|
; GFX10-NEXT: [[ICMP1:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[ADD1]](s32), [[C7]]
|
|
; GFX10-NEXT: G_BRCOND [[ICMP1]](s1), %bb.3
|
|
; GFX10-NEXT: G_BR %bb.4
|
|
; GFX10-NEXT: {{ $}}
|
|
; GFX10-NEXT: bb.4:
|
|
; GFX10-NEXT: successors: %bb.2(0x80000000)
|
|
; GFX10-NEXT: {{ $}}
|
|
; GFX10-NEXT: [[ICMP2:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY5]](s32), [[AMDGPU_BUFFER_LOAD]]
|
|
; GFX10-NEXT: [[OR1:%[0-9]+]]:_(s1) = G_OR [[ICMP]], [[ICMP2]]
|
|
; GFX10-NEXT: [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[OR1]](s1)
|
|
; GFX10-NEXT: [[C10:%[0-9]+]]:_(s1) = G_CONSTANT i1 false
|
|
; GFX10-NEXT: [[COPY6:%[0-9]+]]:sreg_32(s1) = COPY [[C10]](s1)
|
|
; GFX10-NEXT: G_BR %bb.2
|
|
; GFX10-NEXT: {{ $}}
|
|
; GFX10-NEXT: bb.5:
|
|
; GFX10-NEXT: successors: %bb.6(0x80000000)
|
|
; GFX10-NEXT: {{ $}}
|
|
; GFX10-NEXT: [[ZEXT2:%[0-9]+]]:_(s32) = G_ZEXT [[ICMP]](s1)
|
|
; GFX10-NEXT: [[C11:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
|
|
; GFX10-NEXT: [[OR2:%[0-9]+]]:_(s32) = G_OR [[ZEXT2]], [[C11]]
|
|
; GFX10-NEXT: {{ $}}
|
|
; GFX10-NEXT: bb.6:
|
|
; GFX10-NEXT: [[PHI5:%[0-9]+]]:_(s32) = G_PHI [[PHI1]](s32), %bb.2, [[OR2]](s32), %bb.5
|
|
; GFX10-NEXT: [[UV2:%[0-9]+]]:_(<4 x s32>), [[UV3:%[0-9]+]]:_(<4 x s32>) = G_UNMERGE_VALUES [[LOAD]](<8 x s32>)
|
|
; GFX10-NEXT: [[ADD3:%[0-9]+]]:_(s32) = G_ADD [[COPY2]], [[COPY1]]
|
|
; GFX10-NEXT: [[C12:%[0-9]+]]:_(s32) = G_CONSTANT i32 2
|
|
; GFX10-NEXT: [[SHL1:%[0-9]+]]:_(s32) = G_SHL [[ADD3]], [[C12]](s32)
|
|
; GFX10-NEXT: [[C13:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
|
|
; GFX10-NEXT: G_AMDGPU_BUFFER_STORE [[PHI5]](s32), [[UV3]](<4 x s32>), [[C13]](s32), [[SHL1]], [[C13]], 0, 0, 0 :: (dereferenceable store (s32), align 1, addrspace 8)
|
|
; GFX10-NEXT: S_ENDPGM 0
|
|
bb.0:
|
|
successors: %bb.1(0x40000000), %bb.2(0x40000000)
|
|
liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0, $vgpr1, $vgpr2
|
|
|
|
%0:_(s32) = COPY $sgpr0
|
|
%1:_(s32) = COPY $sgpr1
|
|
%2:_(s32) = COPY $vgpr0
|
|
%3:_(s32) = G_IMPLICIT_DEF
|
|
%4:_(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.s.getpc)
|
|
%5:_(s64) = G_CONSTANT i64 -4294967296
|
|
%6:_(s64) = G_AND %4, %5
|
|
%7:_(s64) = G_ZEXT %0(s32)
|
|
%8:_(s64) = G_OR %6, %7
|
|
%9:_(p4) = G_INTTOPTR %8(s64)
|
|
%10:_(<8 x s32>) = G_LOAD %9(p4) :: (invariant load (<8 x s32>), align 16, addrspace 4)
|
|
%11:_(s32) = G_CONSTANT i32 0
|
|
%12:_(s32) = G_CONSTANT i32 1
|
|
%13:_(s32) = G_CONSTANT i32 2
|
|
%14:_(<4 x s32>), %15:_(<4 x s32>) = G_UNMERGE_VALUES %10(<8 x s32>)
|
|
%16:_(s32) = G_CONSTANT i32 -1
|
|
%17:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.mbcnt.lo), %16(s32), %11(s32)
|
|
%18:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.mbcnt.hi), %16(s32), %17(s32)
|
|
%19:_(s32) = G_FREEZE %18
|
|
%20:_(s32) = G_SHL %19, %13(s32)
|
|
%21:_(s32) = G_AMDGPU_BUFFER_LOAD %14(<4 x s32>), %11(s32), %20, %11, 0, 0, 0 :: (dereferenceable load (s32), align 1, addrspace 8)
|
|
%22:_(s1) = G_ICMP intpred(eq), %21(s32), %11
|
|
%23:_(s32) = G_AND %19, %12
|
|
%24:_(s1) = G_TRUNC %23(s32)
|
|
%25:_(s1) = G_CONSTANT i1 true
|
|
%26:_(s1) = G_XOR %24, %25
|
|
G_BRCOND %26(s1), %bb.2
|
|
G_BR %bb.1
|
|
|
|
bb.1:
|
|
successors: %bb.3(0x80000000)
|
|
|
|
%27:_(s32) = G_CONSTANT i32 0
|
|
G_BR %bb.3
|
|
|
|
bb.2:
|
|
successors: %bb.5(0x40000000), %bb.6(0x40000000)
|
|
|
|
%28:_(s32) = G_PHI %29(s32), %bb.4, %3(s32), %bb.0
|
|
%30:_(s1) = G_PHI %31(s1), %bb.4, %25(s1), %bb.0
|
|
G_BRCOND %30(s1), %bb.5
|
|
G_BR %bb.6
|
|
|
|
bb.3:
|
|
successors: %bb.4(0x04000000), %bb.3(0x7c000000)
|
|
|
|
%32:_(s32) = G_PHI %33(s32), %bb.3, %27(s32), %bb.1
|
|
%34:_(s32) = G_PHI %35(s32), %bb.3, %19(s32), %bb.1
|
|
%36:_(s32) = G_PHI %37(s32), %bb.3, %27(s32), %bb.1
|
|
%38:_(s32) = G_CONSTANT i32 0
|
|
%39:_(s32) = G_AMDGPU_BUFFER_LOAD %14(<4 x s32>), %38(s32), %32, %38, 0, 0, 0 :: (dereferenceable load (s32), align 1, addrspace 8)
|
|
%37:_(s32) = G_ADD %39, %36
|
|
%40:_(s32) = G_CONSTANT i32 -1
|
|
%35:_(s32) = G_ADD %34, %40
|
|
%41:_(s32) = G_CONSTANT i32 4
|
|
%33:_(s32) = G_ADD %32, %41
|
|
%42:_(s1) = G_ICMP intpred(ne), %35(s32), %38
|
|
G_BRCOND %42(s1), %bb.3
|
|
G_BR %bb.4
|
|
|
|
bb.4:
|
|
successors: %bb.2(0x80000000)
|
|
|
|
%43:_(s1) = G_ICMP intpred(eq), %37(s32), %21
|
|
%44:_(s1) = G_OR %22, %43
|
|
%29:_(s32) = G_ZEXT %44(s1)
|
|
%31:_(s1) = G_CONSTANT i1 false
|
|
G_BR %bb.2
|
|
|
|
bb.5:
|
|
successors: %bb.6(0x80000000)
|
|
|
|
%45:_(s32) = G_ZEXT %22(s1)
|
|
%46:_(s32) = G_CONSTANT i32 2
|
|
%47:_(s32) = G_OR %45, %46
|
|
|
|
bb.6:
|
|
%48:_(s32) = G_PHI %28(s32), %bb.2, %47(s32), %bb.5
|
|
%49:_(<4 x s32>), %50:_(<4 x s32>) = G_UNMERGE_VALUES %10(<8 x s32>)
|
|
%51:_(s32) = G_ADD %2, %1
|
|
%52:_(s32) = G_CONSTANT i32 2
|
|
%53:_(s32) = G_SHL %51, %52(s32)
|
|
%54:_(s32) = G_CONSTANT i32 0
|
|
G_AMDGPU_BUFFER_STORE %48(s32), %50(<4 x s32>), %54(s32), %53, %54, 0, 0, 0 :: (dereferenceable store (s32), align 1, addrspace 8)
|
|
S_ENDPGM 0
|
|
...
|