TheRock/compiler/amd-llvm/llvm/test/CodeGen/AMDGPU/GlobalISel/fmad.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-amdpal -mcpu=fiji --denormal-fp-math=preserve-sign -o - %s | FileCheck -check-prefix=GFX8 %s
; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 --denormal-fp-math=preserve-sign -o - %s | FileCheck -check-prefix=GFX9 %s
; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-amdpal -mcpu=gfx1010 --denormal-fp-math=preserve-sign -o - %s | FileCheck -check-prefix=GFX10 %s

define amdgpu_ps float @fmad_s32_uniform(float inreg %a, float inreg %b, float inreg %c) {
; GFX8-LABEL: fmad_s32_uniform:
; GFX8:       ; %bb.0:
; GFX8-NEXT:    v_mov_b32_e32 v0, s1
; GFX8-NEXT:    v_mov_b32_e32 v1, s2
; GFX8-NEXT:    v_mad_f32 v0, s0, v0, v1
; GFX8-NEXT:    ; return to shader part epilog
;
; GFX9-LABEL: fmad_s32_uniform:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    v_mov_b32_e32 v0, s1
; GFX9-NEXT:    v_mov_b32_e32 v1, s2
; GFX9-NEXT:    v_mad_f32 v0, s0, v0, v1
; GFX9-NEXT:    ; return to shader part epilog
;
; GFX10-LABEL: fmad_s32_uniform:
; GFX10:       ; %bb.0:
; GFX10-NEXT:    v_mov_b32_e32 v0, s2
; GFX10-NEXT:    v_mad_f32 v0, s1, s0, v0
; GFX10-NEXT:    ; return to shader part epilog
  %mul = fmul float %a, %b
  %result = fadd float %mul, %c
  ret float %result
}

define amdgpu_ps float @fmad_s32_div(float %a, float %b, float %c) {
; GFX8-LABEL: fmad_s32_div:
; GFX8:       ; %bb.0:
; GFX8-NEXT:    v_mad_f32 v0, v0, v1, v2
; GFX8-NEXT:    ; return to shader part epilog
;
; GFX9-LABEL: fmad_s32_div:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    v_mad_f32 v0, v0, v1, v2
; GFX9-NEXT:    ; return to shader part epilog
;
; GFX10-LABEL: fmad_s32_div:
; GFX10:       ; %bb.0:
; GFX10-NEXT:    v_mad_f32 v0, v0, v1, v2
; GFX10-NEXT:    ; return to shader part epilog
  %mul = fmul float %a, %b
  %result = fadd float %mul, %c
  ret float %result
}

define amdgpu_ps half @fmad_s16_uniform(half inreg %a, half inreg %b, half inreg %c) {
; GFX8-LABEL: fmad_s16_uniform:
; GFX8:       ; %bb.0:
; GFX8-NEXT:    v_mov_b32_e32 v0, s1
; GFX8-NEXT:    v_mov_b32_e32 v1, s2
; GFX8-NEXT:    v_mad_f16 v0, s0, v0, v1
; GFX8-NEXT:    ; return to shader part epilog
;
; GFX9-LABEL: fmad_s16_uniform:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    v_mov_b32_e32 v0, s1
; GFX9-NEXT:    v_mov_b32_e32 v1, s2
; GFX9-NEXT:    v_mad_legacy_f16 v0, s0, v0, v1
; GFX9-NEXT:    ; return to shader part epilog
;
; GFX10-LABEL: fmad_s16_uniform:
; GFX10:       ; %bb.0:
; GFX10-NEXT:    v_mul_f16_e64 v0, s0, s1
; GFX10-NEXT:    v_add_f16_e32 v0, s2, v0
; GFX10-NEXT:    ; return to shader part epilog
  %mul = fmul half %a, %b
  %result = fadd half %mul, %c
  ret half %result
}

define amdgpu_ps half @fmad_s16_div(half %a, half %b, half %c) {
; GFX8-LABEL: fmad_s16_div:
; GFX8:       ; %bb.0:
; GFX8-NEXT:    v_mad_f16 v0, v0, v1, v2
; GFX8-NEXT:    ; return to shader part epilog
;
; GFX9-LABEL: fmad_s16_div:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    v_mad_legacy_f16 v0, v0, v1, v2
; GFX9-NEXT:    ; return to shader part epilog
;
; GFX10-LABEL: fmad_s16_div:
; GFX10:       ; %bb.0:
; GFX10-NEXT:    v_mul_f16_e32 v0, v0, v1
; GFX10-NEXT:    v_add_f16_e32 v0, v0, v2
; GFX10-NEXT:    ; return to shader part epilog
  %mul = fmul half %a, %b
  %result = fadd half %mul, %c
  ret half %result
}