derek.holloway
7502bf64a4
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570 lines
26 KiB
LLVM
570 lines
26 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn-amd-amdpal -mattr=-real-true16 -mcpu=gfx1100 -o - %s | FileCheck -check-prefixes=GFX11,GFX11-FAKE16 %s
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; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn-amd-amdpal -mattr=+real-true16 -mcpu=gfx1100 -o - %s | FileCheck -check-prefixes=GFX11,GFX11-TRUE16 %s
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; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn-amd-amdpal -mattr=-real-true16 -mcpu=gfx1200 -o - %s | FileCheck -check-prefixes=GFX12,GFX12-FAKE16 %s
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; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn-amd-amdpal -mattr=+real-true16 -mcpu=gfx1200 -o - %s | FileCheck -check-prefixes=GFX12,GFX12-TRUE16 %s
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; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn-amd-amdpal -mattr=-real-true16 -mcpu=gfx1250 -o - %s | FileCheck -check-prefixes=GFX1250,GFX1250-FAKE16 %s
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; RUN: llc -global-isel -global-isel-abort=2 -mtriple=amdgcn-amd-amdpal -mattr=+real-true16 -mcpu=gfx1250 -o - %s | FileCheck -check-prefixes=GFX1250,GFX1250-TRUE16 %s
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define amdgpu_ps half @fptrunc_f32_to_f16_uniform(float inreg %a) {
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; GFX11-FAKE16-LABEL: fptrunc_f32_to_f16_uniform:
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; GFX11-FAKE16: ; %bb.0:
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; GFX11-FAKE16-NEXT: v_cvt_f16_f32_e32 v0, s0
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; GFX11-FAKE16-NEXT: ; return to shader part epilog
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;
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; GFX11-TRUE16-LABEL: fptrunc_f32_to_f16_uniform:
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; GFX11-TRUE16: ; %bb.0:
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; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, s0
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; GFX11-TRUE16-NEXT: ; return to shader part epilog
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;
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; GFX12-LABEL: fptrunc_f32_to_f16_uniform:
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; GFX12: ; %bb.0:
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; GFX12-NEXT: s_cvt_f16_f32 s0, s0
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; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
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; GFX12-NEXT: v_mov_b32_e32 v0, s0
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; GFX12-NEXT: ; return to shader part epilog
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;
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; GFX1250-LABEL: fptrunc_f32_to_f16_uniform:
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; GFX1250: ; %bb.0:
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; GFX1250-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
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; GFX1250-NEXT: v_nop
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; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
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; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 2, 2), 0 ; msbs: dst=0 src0=0 src1=0 src2=0
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; GFX1250-NEXT: s_cvt_f16_f32 s0, s0
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; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
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; GFX1250-NEXT: v_mov_b32_e32 v0, s0
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; GFX1250-NEXT: ; return to shader part epilog
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%result = fptrunc float %a to half
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ret half %result
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}
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define amdgpu_ps half @fptrunc_f32_to_f16_div(float %a) {
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; GFX11-FAKE16-LABEL: fptrunc_f32_to_f16_div:
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; GFX11-FAKE16: ; %bb.0:
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; GFX11-FAKE16-NEXT: v_cvt_f16_f32_e32 v0, v0
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; GFX11-FAKE16-NEXT: ; return to shader part epilog
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;
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; GFX11-TRUE16-LABEL: fptrunc_f32_to_f16_div:
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; GFX11-TRUE16: ; %bb.0:
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; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v0
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; GFX11-TRUE16-NEXT: ; return to shader part epilog
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;
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; GFX12-FAKE16-LABEL: fptrunc_f32_to_f16_div:
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; GFX12-FAKE16: ; %bb.0:
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; GFX12-FAKE16-NEXT: v_cvt_f16_f32_e32 v0, v0
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; GFX12-FAKE16-NEXT: ; return to shader part epilog
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;
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; GFX12-TRUE16-LABEL: fptrunc_f32_to_f16_div:
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; GFX12-TRUE16: ; %bb.0:
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; GFX12-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v0
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; GFX12-TRUE16-NEXT: ; return to shader part epilog
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;
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; GFX1250-FAKE16-LABEL: fptrunc_f32_to_f16_div:
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; GFX1250-FAKE16: ; %bb.0:
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; GFX1250-FAKE16-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
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; GFX1250-FAKE16-NEXT: v_nop
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; GFX1250-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
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; GFX1250-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 2, 2), 0 ; msbs: dst=0 src0=0 src1=0 src2=0
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; GFX1250-FAKE16-NEXT: v_cvt_f16_f32_e32 v0, v0
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; GFX1250-FAKE16-NEXT: ; return to shader part epilog
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;
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; GFX1250-TRUE16-LABEL: fptrunc_f32_to_f16_div:
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; GFX1250-TRUE16: ; %bb.0:
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; GFX1250-TRUE16-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
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; GFX1250-TRUE16-NEXT: v_nop
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; GFX1250-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
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; GFX1250-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 2, 2), 0 ; msbs: dst=0 src0=0 src1=0 src2=0
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; GFX1250-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v0
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; GFX1250-TRUE16-NEXT: ; return to shader part epilog
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%result = fptrunc float %a to half
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ret half %result
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}
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define amdgpu_ps float @fptrunc_f64_to_f32_uniform(double inreg %a) {
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; GFX11-LABEL: fptrunc_f64_to_f32_uniform:
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; GFX11: ; %bb.0:
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; GFX11-NEXT: v_cvt_f32_f64_e32 v0, s[0:1]
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; GFX11-NEXT: ; return to shader part epilog
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;
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; GFX12-LABEL: fptrunc_f64_to_f32_uniform:
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; GFX12: ; %bb.0:
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; GFX12-NEXT: v_cvt_f32_f64_e32 v0, s[0:1]
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; GFX12-NEXT: ; return to shader part epilog
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;
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; GFX1250-LABEL: fptrunc_f64_to_f32_uniform:
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; GFX1250: ; %bb.0:
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; GFX1250-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
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; GFX1250-NEXT: v_nop
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; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
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; GFX1250-NEXT: v_cvt_f32_f64_e32 v0, s[0:1]
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; GFX1250-NEXT: ; return to shader part epilog
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%result = fptrunc double %a to float
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ret float %result
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}
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define amdgpu_ps float @fptrunc_f64_to_f32_div(double %a) {
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; GFX11-LABEL: fptrunc_f64_to_f32_div:
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; GFX11: ; %bb.0:
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; GFX11-NEXT: v_cvt_f32_f64_e32 v0, v[0:1]
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; GFX11-NEXT: ; return to shader part epilog
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;
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; GFX12-LABEL: fptrunc_f64_to_f32_div:
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; GFX12: ; %bb.0:
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; GFX12-NEXT: v_cvt_f32_f64_e32 v0, v[0:1]
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; GFX12-NEXT: ; return to shader part epilog
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;
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; GFX1250-LABEL: fptrunc_f64_to_f32_div:
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; GFX1250: ; %bb.0:
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; GFX1250-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
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; GFX1250-NEXT: v_nop
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; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
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; GFX1250-NEXT: v_cvt_f32_f64_e32 v0, v[0:1]
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; GFX1250-NEXT: ; return to shader part epilog
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%result = fptrunc double %a to float
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ret float %result
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}
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define amdgpu_ps half @fptrunc_f64_to_f16_uniform(double inreg %a) {
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; GFX11-LABEL: fptrunc_f64_to_f16_uniform:
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; GFX11: ; %bb.0:
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; GFX11-NEXT: s_bfe_u32 s2, s1, 0xb0014
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; GFX11-NEXT: s_lshr_b32 s3, s1, 8
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; GFX11-NEXT: s_and_b32 s4, s1, 0x1ff
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; GFX11-NEXT: s_addk_i32 s2, 0xfc10
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; GFX11-NEXT: s_and_b32 s3, s3, 0xffe
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; GFX11-NEXT: s_or_b32 s0, s4, s0
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; GFX11-NEXT: s_cselect_b32 s0, 1, 0
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; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
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; GFX11-NEXT: s_or_b32 s0, s3, s0
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; GFX11-NEXT: s_cselect_b32 s3, 1, 0
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; GFX11-NEXT: s_sub_i32 s4, 1, s2
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; GFX11-NEXT: s_or_b32 s5, s0, 0x1000
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; GFX11-NEXT: s_max_i32 s4, s4, 0
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; GFX11-NEXT: s_lshl_b32 s3, s3, 9
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; GFX11-NEXT: s_min_i32 s4, s4, 13
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; GFX11-NEXT: s_lshl_b32 s7, s2, 12
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; GFX11-NEXT: s_lshr_b32 s6, s5, s4
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; GFX11-NEXT: s_or_b32 s3, s3, 0x7c00
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; GFX11-NEXT: s_lshl_b32 s4, s6, s4
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; GFX11-NEXT: s_or_b32 s0, s0, s7
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; GFX11-NEXT: s_cmp_lg_u32 s4, s5
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; GFX11-NEXT: s_cselect_b32 s4, 1, 0
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; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
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; GFX11-NEXT: s_or_b32 s4, s6, s4
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; GFX11-NEXT: s_cmp_lt_i32 s2, 1
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; GFX11-NEXT: s_cselect_b32 s0, s4, s0
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; GFX11-NEXT: s_and_b32 s4, s0, 7
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; GFX11-NEXT: s_lshr_b32 s0, s0, 2
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; GFX11-NEXT: s_cmp_eq_u32 s4, 3
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; GFX11-NEXT: s_cselect_b32 s5, 1, 0
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; GFX11-NEXT: s_cmp_gt_i32 s4, 5
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; GFX11-NEXT: s_cselect_b32 s4, 1, 0
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; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
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; GFX11-NEXT: s_or_b32 s4, s5, s4
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; GFX11-NEXT: s_add_i32 s0, s0, s4
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; GFX11-NEXT: s_cmp_gt_i32 s2, 30
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; GFX11-NEXT: s_cselect_b32 s0, 0x7c00, s0
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; GFX11-NEXT: s_cmpk_eq_i32 s2, 0x40f
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; GFX11-NEXT: s_cselect_b32 s0, s3, s0
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; GFX11-NEXT: s_lshr_b32 s1, s1, 16
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; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
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; GFX11-NEXT: s_and_b32 s1, s1, 0x8000
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; GFX11-NEXT: s_or_b32 s0, s1, s0
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; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
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; GFX11-NEXT: v_mov_b32_e32 v0, s0
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; GFX11-NEXT: ; return to shader part epilog
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;
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; GFX12-LABEL: fptrunc_f64_to_f16_uniform:
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; GFX12: ; %bb.0:
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; GFX12-NEXT: s_bfe_u32 s2, s1, 0xb0014
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; GFX12-NEXT: s_lshr_b32 s3, s1, 8
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; GFX12-NEXT: s_and_b32 s4, s1, 0x1ff
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; GFX12-NEXT: s_addk_co_i32 s2, 0xfc10
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; GFX12-NEXT: s_and_b32 s3, s3, 0xffe
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; GFX12-NEXT: s_or_b32 s0, s4, s0
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; GFX12-NEXT: s_cselect_b32 s0, 1, 0
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; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
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; GFX12-NEXT: s_or_b32 s0, s3, s0
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; GFX12-NEXT: s_cselect_b32 s3, 1, 0
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; GFX12-NEXT: s_sub_co_i32 s4, 1, s2
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; GFX12-NEXT: s_or_b32 s5, s0, 0x1000
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; GFX12-NEXT: s_max_i32 s4, s4, 0
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; GFX12-NEXT: s_lshl_b32 s3, s3, 9
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; GFX12-NEXT: s_min_i32 s4, s4, 13
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; GFX12-NEXT: s_lshl_b32 s7, s2, 12
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; GFX12-NEXT: s_lshr_b32 s6, s5, s4
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; GFX12-NEXT: s_or_b32 s3, s3, 0x7c00
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; GFX12-NEXT: s_lshl_b32 s4, s6, s4
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; GFX12-NEXT: s_or_b32 s0, s0, s7
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; GFX12-NEXT: s_cmp_lg_u32 s4, s5
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; GFX12-NEXT: s_cselect_b32 s4, 1, 0
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; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
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; GFX12-NEXT: s_or_b32 s4, s6, s4
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; GFX12-NEXT: s_cmp_lt_i32 s2, 1
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; GFX12-NEXT: s_cselect_b32 s0, s4, s0
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; GFX12-NEXT: s_and_b32 s4, s0, 7
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; GFX12-NEXT: s_lshr_b32 s0, s0, 2
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; GFX12-NEXT: s_cmp_eq_u32 s4, 3
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; GFX12-NEXT: s_cselect_b32 s5, 1, 0
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; GFX12-NEXT: s_cmp_gt_i32 s4, 5
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; GFX12-NEXT: s_cselect_b32 s4, 1, 0
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; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
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; GFX12-NEXT: s_or_b32 s4, s5, s4
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; GFX12-NEXT: s_add_co_i32 s0, s0, s4
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; GFX12-NEXT: s_cmp_gt_i32 s2, 30
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; GFX12-NEXT: s_cselect_b32 s0, 0x7c00, s0
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; GFX12-NEXT: s_cmp_eq_u32 s2, 0x40f
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; GFX12-NEXT: s_cselect_b32 s0, s3, s0
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; GFX12-NEXT: s_lshr_b32 s1, s1, 16
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; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
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; GFX12-NEXT: s_and_b32 s1, s1, 0x8000
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; GFX12-NEXT: s_or_b32 s0, s1, s0
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; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
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; GFX12-NEXT: v_mov_b32_e32 v0, s0
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; GFX12-NEXT: ; return to shader part epilog
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;
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; GFX1250-LABEL: fptrunc_f64_to_f16_uniform:
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; GFX1250: ; %bb.0:
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; GFX1250-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
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; GFX1250-NEXT: v_nop
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; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
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; GFX1250-NEXT: s_bfe_u32 s2, s1, 0xb0014
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; GFX1250-NEXT: s_lshr_b32 s3, s1, 8
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; GFX1250-NEXT: s_and_b32 s4, s1, 0x1ff
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; GFX1250-NEXT: s_addk_co_i32 s2, 0xfc10
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; GFX1250-NEXT: s_and_b32 s3, s3, 0xffe
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; GFX1250-NEXT: s_or_b32 s0, s4, s0
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; GFX1250-NEXT: s_cselect_b32 s0, 1, 0
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; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
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; GFX1250-NEXT: s_or_b32 s0, s3, s0
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; GFX1250-NEXT: s_cselect_b32 s3, 1, 0
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; GFX1250-NEXT: s_sub_co_i32 s4, 1, s2
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; GFX1250-NEXT: s_or_b32 s5, s0, 0x1000
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; GFX1250-NEXT: s_max_i32 s4, s4, 0
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; GFX1250-NEXT: s_lshl_b32 s3, s3, 9
|
|
; GFX1250-NEXT: s_min_i32 s4, s4, 13
|
|
; GFX1250-NEXT: s_lshl_b32 s7, s2, 12
|
|
; GFX1250-NEXT: s_lshr_b32 s6, s5, s4
|
|
; GFX1250-NEXT: s_or_b32 s3, s3, 0x7c00
|
|
; GFX1250-NEXT: s_lshl_b32 s4, s6, s4
|
|
; GFX1250-NEXT: s_or_b32 s0, s0, s7
|
|
; GFX1250-NEXT: s_cmp_lg_u32 s4, s5
|
|
; GFX1250-NEXT: s_cselect_b32 s4, 1, 0
|
|
; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
|
|
; GFX1250-NEXT: s_or_b32 s4, s6, s4
|
|
; GFX1250-NEXT: s_cmp_lt_i32 s2, 1
|
|
; GFX1250-NEXT: s_cselect_b32 s0, s4, s0
|
|
; GFX1250-NEXT: s_and_b32 s4, s0, 7
|
|
; GFX1250-NEXT: s_lshr_b32 s0, s0, 2
|
|
; GFX1250-NEXT: s_cmp_eq_u32 s4, 3
|
|
; GFX1250-NEXT: s_cselect_b32 s5, 1, 0
|
|
; GFX1250-NEXT: s_cmp_gt_i32 s4, 5
|
|
; GFX1250-NEXT: s_cselect_b32 s4, 1, 0
|
|
; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
|
|
; GFX1250-NEXT: s_or_b32 s4, s5, s4
|
|
; GFX1250-NEXT: s_add_co_i32 s0, s0, s4
|
|
; GFX1250-NEXT: s_cmp_gt_i32 s2, 30
|
|
; GFX1250-NEXT: s_cselect_b32 s0, 0x7c00, s0
|
|
; GFX1250-NEXT: s_cmp_eq_u32 s2, 0x40f
|
|
; GFX1250-NEXT: s_cselect_b32 s0, s3, s0
|
|
; GFX1250-NEXT: s_lshr_b32 s1, s1, 16
|
|
; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
|
|
; GFX1250-NEXT: s_and_b32 s1, s1, 0x8000
|
|
; GFX1250-NEXT: s_or_b32 s0, s1, s0
|
|
; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
|
|
; GFX1250-NEXT: v_mov_b32_e32 v0, s0
|
|
; GFX1250-NEXT: ; return to shader part epilog
|
|
%result = fptrunc double %a to half
|
|
ret half %result
|
|
}
|
|
|
|
define amdgpu_ps half @fptrunc_f64_to_f16_div(double %a) {
|
|
; GFX11-LABEL: fptrunc_f64_to_f16_div:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: v_and_or_b32 v0, 0x1ff, v1, v0
|
|
; GFX11-NEXT: v_bfe_u32 v2, v1, 20, 11
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v3, 8, v1
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v1, 16, v1
|
|
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
|
|
; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
|
|
; GFX11-NEXT: v_add_nc_u32_e32 v2, 0xfffffc10, v2
|
|
; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
|
|
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
|
|
; GFX11-NEXT: v_sub_nc_u32_e32 v4, 1, v2
|
|
; GFX11-NEXT: v_and_or_b32 v0, 0xffe, v3, v0
|
|
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
|
|
; GFX11-NEXT: v_med3_i32 v3, v4, 0, 13
|
|
; GFX11-NEXT: v_or_b32_e32 v4, 0x1000, v0
|
|
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v5, v3, v4
|
|
; GFX11-NEXT: v_lshlrev_b32_e32 v3, v3, v5
|
|
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
|
|
; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, v3, v4
|
|
; GFX11-NEXT: v_lshl_or_b32 v4, v2, 12, v0
|
|
; GFX11-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc_lo
|
|
; GFX11-NEXT: v_cmp_gt_i32_e32 vcc_lo, 1, v2
|
|
; GFX11-NEXT: v_or_b32_e32 v3, v5, v3
|
|
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
|
|
; GFX11-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc_lo
|
|
; GFX11-NEXT: v_and_b32_e32 v4, 7, v3
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v3, 2, v3
|
|
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2)
|
|
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v4
|
|
; GFX11-NEXT: v_cmp_lt_i32_e64 s0, 5, v4
|
|
; GFX11-NEXT: s_or_b32 s0, vcc_lo, s0
|
|
; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
|
|
; GFX11-NEXT: v_cndmask_b32_e64 v4, 0, 1, s0
|
|
; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
|
|
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
|
|
; GFX11-NEXT: v_add_nc_u32_e32 v3, v3, v4
|
|
; GFX11-NEXT: v_cmp_lt_i32_e32 vcc_lo, 30, v2
|
|
; GFX11-NEXT: v_lshl_or_b32 v0, v0, 9, 0x7c00
|
|
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
|
|
; GFX11-NEXT: v_cndmask_b32_e64 v3, v3, 0x7c00, vcc_lo
|
|
; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0x40f, v2
|
|
; GFX11-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc_lo
|
|
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX11-NEXT: v_and_or_b32 v0, 0x8000, v1, v0
|
|
; GFX11-NEXT: ; return to shader part epilog
|
|
;
|
|
; GFX12-LABEL: fptrunc_f64_to_f16_div:
|
|
; GFX12: ; %bb.0:
|
|
; GFX12-NEXT: v_and_or_b32 v0, 0x1ff, v1, v0
|
|
; GFX12-NEXT: v_bfe_u32 v2, v1, 20, 11
|
|
; GFX12-NEXT: v_lshrrev_b32_e32 v3, 8, v1
|
|
; GFX12-NEXT: v_lshrrev_b32_e32 v1, 16, v1
|
|
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
|
|
; GFX12-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
|
|
; GFX12-NEXT: v_add_nc_u32_e32 v2, 0xfffffc10, v2
|
|
; GFX12-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
|
|
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
|
|
; GFX12-NEXT: v_sub_nc_u32_e32 v4, 1, v2
|
|
; GFX12-NEXT: v_and_or_b32 v0, 0xffe, v3, v0
|
|
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
|
|
; GFX12-NEXT: v_med3_i32 v3, v4, 0, 13
|
|
; GFX12-NEXT: v_or_b32_e32 v4, 0x1000, v0
|
|
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
|
|
; GFX12-NEXT: v_lshrrev_b32_e32 v5, v3, v4
|
|
; GFX12-NEXT: v_lshlrev_b32_e32 v3, v3, v5
|
|
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2)
|
|
; GFX12-NEXT: v_cmp_ne_u32_e32 vcc_lo, v3, v4
|
|
; GFX12-NEXT: v_lshl_or_b32 v4, v2, 12, v0
|
|
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
|
|
; GFX12-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc_lo
|
|
; GFX12-NEXT: v_cmp_gt_i32_e32 vcc_lo, 1, v2
|
|
; GFX12-NEXT: v_or_b32_e32 v3, v5, v3
|
|
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
|
|
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
|
|
; GFX12-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc_lo
|
|
; GFX12-NEXT: v_and_b32_e32 v4, 7, v3
|
|
; GFX12-NEXT: v_lshrrev_b32_e32 v3, 2, v3
|
|
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2)
|
|
; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v4
|
|
; GFX12-NEXT: v_cmp_lt_i32_e64 s0, 5, v4
|
|
; GFX12-NEXT: s_or_b32 s0, vcc_lo, s0
|
|
; GFX12-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
|
|
; GFX12-NEXT: v_cndmask_b32_e64 v4, 0, 1, s0
|
|
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
|
|
; GFX12-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
|
|
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
|
|
; GFX12-NEXT: v_add_nc_u32_e32 v3, v3, v4
|
|
; GFX12-NEXT: v_cmp_lt_i32_e32 vcc_lo, 30, v2
|
|
; GFX12-NEXT: v_lshl_or_b32 v0, v0, 9, 0x7c00
|
|
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
|
|
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
|
|
; GFX12-NEXT: v_cndmask_b32_e64 v3, v3, 0x7c00, vcc_lo
|
|
; GFX12-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0x40f, v2
|
|
; GFX12-NEXT: s_wait_alu depctr_va_vcc(0)
|
|
; GFX12-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc_lo
|
|
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX12-NEXT: v_and_or_b32 v0, 0x8000, v1, v0
|
|
; GFX12-NEXT: ; return to shader part epilog
|
|
;
|
|
; GFX1250-LABEL: fptrunc_f64_to_f16_div:
|
|
; GFX1250: ; %bb.0:
|
|
; GFX1250-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
|
|
; GFX1250-NEXT: v_nop
|
|
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
|
|
; GFX1250-NEXT: v_and_or_b32 v0, 0x1ff, v1, v0
|
|
; GFX1250-NEXT: v_bfe_u32 v2, v1, 20, 11
|
|
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
|
|
; GFX1250-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
|
|
; GFX1250-NEXT: v_add_nc_u32_e32 v2, 0xfffffc10, v2
|
|
; GFX1250-NEXT: v_dual_lshrrev_b32 v3, 8, v1 :: v_dual_lshrrev_b32 v1, 16, v1
|
|
; GFX1250-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
|
|
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
|
|
; GFX1250-NEXT: v_sub_nc_u32_e32 v4, 1, v2
|
|
; GFX1250-NEXT: v_and_or_b32 v0, 0xffe, v3, v0
|
|
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
|
|
; GFX1250-NEXT: v_med3_i32 v3, v4, 0, 13
|
|
; GFX1250-NEXT: v_or_b32_e32 v4, 0x1000, v0
|
|
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
|
|
; GFX1250-NEXT: v_lshrrev_b32_e32 v5, v3, v4
|
|
; GFX1250-NEXT: v_lshlrev_b32_e32 v3, v3, v5
|
|
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
|
|
; GFX1250-NEXT: v_cmp_ne_u32_e32 vcc_lo, v3, v4
|
|
; GFX1250-NEXT: v_lshl_or_b32 v4, v2, 12, v0
|
|
; GFX1250-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc_lo
|
|
; GFX1250-NEXT: v_cmp_gt_i32_e32 vcc_lo, 1, v2
|
|
; GFX1250-NEXT: v_or_b32_e32 v3, v5, v3
|
|
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
|
|
; GFX1250-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc_lo
|
|
; GFX1250-NEXT: v_and_b32_e32 v4, 7, v3
|
|
; GFX1250-NEXT: v_lshrrev_b32_e32 v3, 2, v3
|
|
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2)
|
|
; GFX1250-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v4
|
|
; GFX1250-NEXT: v_cmp_lt_i32_e64 s0, 5, v4
|
|
; GFX1250-NEXT: s_or_b32 s0, vcc_lo, s0
|
|
; GFX1250-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
|
|
; GFX1250-NEXT: v_cndmask_b32_e64 v4, 0, 1, s0
|
|
; GFX1250-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
|
|
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
|
|
; GFX1250-NEXT: v_add_nc_u32_e32 v3, v3, v4
|
|
; GFX1250-NEXT: v_cmp_lt_i32_e32 vcc_lo, 30, v2
|
|
; GFX1250-NEXT: v_lshl_or_b32 v0, v0, 9, 0x7c00
|
|
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
|
|
; GFX1250-NEXT: v_cndmask_b32_e64 v3, v3, 0x7c00, vcc_lo
|
|
; GFX1250-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0x40f, v2
|
|
; GFX1250-NEXT: v_cndmask_b32_e32 v0, v3, v0, vcc_lo
|
|
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX1250-NEXT: v_and_or_b32 v0, 0x8000, v1, v0
|
|
; GFX1250-NEXT: ; return to shader part epilog
|
|
%result = fptrunc double %a to half
|
|
ret half %result
|
|
}
|
|
|
|
define amdgpu_ps <2 x half> @fptrunc_v2f32_to_v2f16_uniform(<2 x float> inreg %a) {
|
|
; GFX11-FAKE16-LABEL: fptrunc_v2f32_to_v2f16_uniform:
|
|
; GFX11-FAKE16: ; %bb.0:
|
|
; GFX11-FAKE16-NEXT: v_cvt_f16_f32_e32 v0, s0
|
|
; GFX11-FAKE16-NEXT: v_cvt_f16_f32_e32 v1, s1
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX11-FAKE16-NEXT: v_pack_b32_f16 v0, v0, v1
|
|
; GFX11-FAKE16-NEXT: ; return to shader part epilog
|
|
;
|
|
; GFX11-TRUE16-LABEL: fptrunc_v2f32_to_v2f16_uniform:
|
|
; GFX11-TRUE16: ; %bb.0:
|
|
; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, s0
|
|
; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.h, s1
|
|
; GFX11-TRUE16-NEXT: ; return to shader part epilog
|
|
;
|
|
; GFX12-LABEL: fptrunc_v2f32_to_v2f16_uniform:
|
|
; GFX12: ; %bb.0:
|
|
; GFX12-NEXT: s_cvt_f16_f32 s0, s0
|
|
; GFX12-NEXT: s_cvt_f16_f32 s1, s1
|
|
; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_3) | instskip(NEXT) | instid1(SALU_CYCLE_1)
|
|
; GFX12-NEXT: s_pack_ll_b32_b16 s0, s0, s1
|
|
; GFX12-NEXT: v_mov_b32_e32 v0, s0
|
|
; GFX12-NEXT: ; return to shader part epilog
|
|
;
|
|
; GFX1250-LABEL: fptrunc_v2f32_to_v2f16_uniform:
|
|
; GFX1250: ; %bb.0:
|
|
; GFX1250-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
|
|
; GFX1250-NEXT: v_nop
|
|
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
|
|
; GFX1250-NEXT: v_mov_b64_e32 v[0:1], s[0:1]
|
|
; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX1250-NEXT: v_cvt_pk_f16_f32 v0, v0, v1
|
|
; GFX1250-NEXT: ; return to shader part epilog
|
|
%result = fptrunc <2 x float> %a to <2 x half>
|
|
ret <2 x half> %result
|
|
}
|
|
|
|
define amdgpu_ps <2 x half> @fptrunc_v2f32_to_v2f16_div(<2 x float> %a) {
|
|
; GFX11-FAKE16-LABEL: fptrunc_v2f32_to_v2f16_div:
|
|
; GFX11-FAKE16: ; %bb.0:
|
|
; GFX11-FAKE16-NEXT: v_cvt_f16_f32_e32 v0, v0
|
|
; GFX11-FAKE16-NEXT: v_cvt_f16_f32_e32 v1, v1
|
|
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX11-FAKE16-NEXT: v_pack_b32_f16 v0, v0, v1
|
|
; GFX11-FAKE16-NEXT: ; return to shader part epilog
|
|
;
|
|
; GFX11-TRUE16-LABEL: fptrunc_v2f32_to_v2f16_div:
|
|
; GFX11-TRUE16: ; %bb.0:
|
|
; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v0
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; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.h, v1
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; GFX11-TRUE16-NEXT: ; return to shader part epilog
|
|
;
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|
; GFX12-FAKE16-LABEL: fptrunc_v2f32_to_v2f16_div:
|
|
; GFX12-FAKE16: ; %bb.0:
|
|
; GFX12-FAKE16-NEXT: v_cvt_f16_f32_e32 v0, v0
|
|
; GFX12-FAKE16-NEXT: v_cvt_f16_f32_e32 v1, v1
|
|
; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX12-FAKE16-NEXT: v_pack_b32_f16 v0, v0, v1
|
|
; GFX12-FAKE16-NEXT: ; return to shader part epilog
|
|
;
|
|
; GFX12-TRUE16-LABEL: fptrunc_v2f32_to_v2f16_div:
|
|
; GFX12-TRUE16: ; %bb.0:
|
|
; GFX12-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v0
|
|
; GFX12-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.h, v1
|
|
; GFX12-TRUE16-NEXT: ; return to shader part epilog
|
|
;
|
|
; GFX1250-LABEL: fptrunc_v2f32_to_v2f16_div:
|
|
; GFX1250: ; %bb.0:
|
|
; GFX1250-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
|
|
; GFX1250-NEXT: v_nop
|
|
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
|
|
; GFX1250-NEXT: v_cvt_pk_f16_f32 v0, v0, v1
|
|
; GFX1250-NEXT: ; return to shader part epilog
|
|
%result = fptrunc <2 x float> %a to <2 x half>
|
|
ret <2 x half> %result
|
|
}
|
|
|
|
define amdgpu_ps void @fptrunc_v2f64_to_v2f32_uniform(<2 x double> inreg %a, ptr addrspace(1) %ptr) {
|
|
; GFX11-LABEL: fptrunc_v2f64_to_v2f32_uniform:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: v_cvt_f32_f64_e32 v2, s[0:1]
|
|
; GFX11-NEXT: v_cvt_f32_f64_e32 v3, s[2:3]
|
|
; GFX11-NEXT: global_store_b64 v[0:1], v[2:3], off
|
|
; GFX11-NEXT: s_endpgm
|
|
;
|
|
; GFX12-LABEL: fptrunc_v2f64_to_v2f32_uniform:
|
|
; GFX12: ; %bb.0:
|
|
; GFX12-NEXT: v_cvt_f32_f64_e32 v2, s[0:1]
|
|
; GFX12-NEXT: v_cvt_f32_f64_e32 v3, s[2:3]
|
|
; GFX12-NEXT: global_store_b64 v[0:1], v[2:3], off
|
|
; GFX12-NEXT: s_endpgm
|
|
;
|
|
; GFX1250-LABEL: fptrunc_v2f64_to_v2f32_uniform:
|
|
; GFX1250: ; %bb.0:
|
|
; GFX1250-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
|
|
; GFX1250-NEXT: v_nop
|
|
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
|
|
; GFX1250-NEXT: v_cvt_f32_f64_e32 v2, s[0:1]
|
|
; GFX1250-NEXT: v_cvt_f32_f64_e32 v3, s[2:3]
|
|
; GFX1250-NEXT: global_store_b64 v[0:1], v[2:3], off
|
|
; GFX1250-NEXT: s_endpgm
|
|
%result = fptrunc <2 x double> %a to <2 x float>
|
|
store <2 x float> %result, ptr addrspace(1) %ptr
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_ps void @fptrunc_v2f64_to_v2f32_div(<2 x double> %a, ptr addrspace(1) %ptr) {
|
|
; GFX11-LABEL: fptrunc_v2f64_to_v2f32_div:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: v_cvt_f32_f64_e32 v0, v[0:1]
|
|
; GFX11-NEXT: v_cvt_f32_f64_e32 v1, v[2:3]
|
|
; GFX11-NEXT: global_store_b64 v[4:5], v[0:1], off
|
|
; GFX11-NEXT: s_endpgm
|
|
;
|
|
; GFX12-LABEL: fptrunc_v2f64_to_v2f32_div:
|
|
; GFX12: ; %bb.0:
|
|
; GFX12-NEXT: v_cvt_f32_f64_e32 v0, v[0:1]
|
|
; GFX12-NEXT: v_cvt_f32_f64_e32 v1, v[2:3]
|
|
; GFX12-NEXT: global_store_b64 v[4:5], v[0:1], off
|
|
; GFX12-NEXT: s_endpgm
|
|
;
|
|
; GFX1250-LABEL: fptrunc_v2f64_to_v2f32_div:
|
|
; GFX1250: ; %bb.0:
|
|
; GFX1250-NEXT: global_prefetch_b8 v0, s[0:1] scope:SCOPE_SE
|
|
; GFX1250-NEXT: v_nop
|
|
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
|
|
; GFX1250-NEXT: v_cvt_f32_f64_e32 v0, v[0:1]
|
|
; GFX1250-NEXT: v_cvt_f32_f64_e32 v1, v[2:3]
|
|
; GFX1250-NEXT: global_store_b64 v[4:5], v[0:1], off
|
|
; GFX1250-NEXT: s_endpgm
|
|
%result = fptrunc <2 x double> %a to <2 x float>
|
|
store <2 x float> %result, ptr addrspace(1) %ptr
|
|
ret void
|
|
}
|