derek.holloway
7502bf64a4
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239 lines
13 KiB
YAML
239 lines
13 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefix=WAVE32 %s
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# RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefix=WAVE64 %s
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# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefixes=GFX11-TRUE16 %s
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# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck -check-prefixes=GFX11-FAKE16 %s
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# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -global-isel -start-before=instruction-select -stop-after=reg-usage-propagation -verify-machineinstrs %s -o - | FileCheck -check-prefixes=GFX11-FOLD-TRUE16 %s
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# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -global-isel -start-before=instruction-select -stop-after=reg-usage-propagation -verify-machineinstrs %s -o - | FileCheck -check-prefixes=GFX11-FOLD-FAKE16 %s
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# RUN: llc -mtriple=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=2 -pass-remarks-missed='gisel*' %s -filetype=null 2>&1 | FileCheck -check-prefix=SI-ERR %s
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# SI-ERR-NOT: remark
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# SI-ERR: remark: <unknown>:0:0: cannot select: %3:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), %2:sgpr(s16), %1:vgpr(s32) (in function: class_s16_vcc_sv)
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# SI-ERR-NEXT: remark: <unknown>:0:0: cannot select: %3:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), %2:vgpr(s16), %1:sgpr(s32) (in function: class_s16_vcc_vs)
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# SI-ERR-NEXT: remark: <unknown>:0:0: cannot select: %3:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), %2:vgpr(s16), %1:vgpr(s32) (in function: class_s16_vcc_vv)
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# SI-ERR-NOT: remark
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---
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name: class_s16_vcc_sv
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr0, $vgpr0
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; WAVE32-LABEL: name: class_s16_vcc_sv
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; WAVE32: liveins: $sgpr0, $vgpr0
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; WAVE32-NEXT: {{ $}}
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; WAVE32-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; WAVE32-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; WAVE32-NEXT: [[V_CMP_CLASS_F16_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_CLASS_F16_e64 0, [[COPY]], [[COPY1]], implicit $exec
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; WAVE32-NEXT: S_ENDPGM 0, implicit [[V_CMP_CLASS_F16_e64_]]
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;
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; WAVE64-LABEL: name: class_s16_vcc_sv
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; WAVE64: liveins: $sgpr0, $vgpr0
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; WAVE64-NEXT: {{ $}}
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; WAVE64-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; WAVE64-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; WAVE64-NEXT: [[V_CMP_CLASS_F16_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_CLASS_F16_e64 0, [[COPY]], [[COPY1]], implicit $exec
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; WAVE64-NEXT: S_ENDPGM 0, implicit [[V_CMP_CLASS_F16_e64_]]
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;
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; GFX11-TRUE16-LABEL: name: class_s16_vcc_sv
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; GFX11-TRUE16: liveins: $sgpr0, $vgpr0
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; GFX11-TRUE16-NEXT: {{ $}}
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; GFX11-TRUE16-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; GFX11-TRUE16-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GFX11-TRUE16-NEXT: [[COPY2:%[0-9]+]]:vgpr_16 = COPY [[COPY1]].lo16
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; GFX11-TRUE16-NEXT: [[V_CMP_CLASS_F16_t16_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_CLASS_F16_t16_e64 0, [[COPY]], 0, [[COPY2]], 0, implicit $exec
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; GFX11-TRUE16-NEXT: S_ENDPGM 0, implicit [[V_CMP_CLASS_F16_t16_e64_]]
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;
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; GFX11-FAKE16-LABEL: name: class_s16_vcc_sv
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; GFX11-FAKE16: liveins: $sgpr0, $vgpr0
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; GFX11-FAKE16-NEXT: {{ $}}
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; GFX11-FAKE16-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; GFX11-FAKE16-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GFX11-FAKE16-NEXT: [[V_CMP_CLASS_F16_fake16_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_CLASS_F16_fake16_e64 0, [[COPY]], 0, [[COPY1]], implicit $exec
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; GFX11-FAKE16-NEXT: S_ENDPGM 0, implicit [[V_CMP_CLASS_F16_fake16_e64_]]
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;
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; GFX11-FOLD-TRUE16-LABEL: name: class_s16_vcc_sv
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; GFX11-FOLD-TRUE16: liveins: $sgpr0, $vgpr0
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; GFX11-FOLD-TRUE16-NEXT: {{ $}}
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; GFX11-FOLD-TRUE16-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; GFX11-FOLD-TRUE16-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GFX11-FOLD-TRUE16-NEXT: [[V_CMP_CLASS_F16_t16_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_CLASS_F16_t16_e64 0, [[COPY]], 0, [[COPY1]].lo16, 0, implicit $exec
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; GFX11-FOLD-TRUE16-NEXT: S_ENDPGM 0, implicit [[V_CMP_CLASS_F16_t16_e64_]]
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;
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; GFX11-FOLD-FAKE16-LABEL: name: class_s16_vcc_sv
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; GFX11-FOLD-FAKE16: liveins: $sgpr0, $vgpr0
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; GFX11-FOLD-FAKE16-NEXT: {{ $}}
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; GFX11-FOLD-FAKE16-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; GFX11-FOLD-FAKE16-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GFX11-FOLD-FAKE16-NEXT: [[V_CMP_CLASS_F16_fake16_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_CLASS_F16_fake16_e64 0, [[COPY]], 0, [[COPY1]], implicit $exec
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; GFX11-FOLD-FAKE16-NEXT: S_ENDPGM 0, implicit [[V_CMP_CLASS_F16_fake16_e64_]]
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;
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; SI-ERR-LABEL: name: class_s16_vcc_sv
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; SI-ERR: liveins: $sgpr0, $vgpr0
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; SI-ERR-NEXT: {{ $}}
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; SI-ERR-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
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; SI-ERR-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
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; SI-ERR-NEXT: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY]](s32)
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; SI-ERR-NEXT: [[INT:%[0-9]+]]:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), [[TRUNC]](s16), [[COPY1]](s32)
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; SI-ERR-NEXT: S_ENDPGM 0, implicit [[INT]](s1)
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%0:sgpr(s32) = COPY $sgpr0
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%1:vgpr(s32) = COPY $vgpr0
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%2:sgpr(s16) = G_TRUNC %0
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%4:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), %2, %1
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S_ENDPGM 0, implicit %4
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...
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---
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name: class_s16_vcc_vs
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr0, $vgpr0
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; WAVE32-LABEL: name: class_s16_vcc_vs
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; WAVE32: liveins: $sgpr0, $vgpr0
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; WAVE32-NEXT: {{ $}}
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; WAVE32-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; WAVE32-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; WAVE32-NEXT: [[V_CMP_CLASS_F16_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_CLASS_F16_e64 0, [[COPY]], [[COPY1]], implicit $exec
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; WAVE32-NEXT: S_ENDPGM 0, implicit [[V_CMP_CLASS_F16_e64_]]
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;
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; WAVE64-LABEL: name: class_s16_vcc_vs
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; WAVE64: liveins: $sgpr0, $vgpr0
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; WAVE64-NEXT: {{ $}}
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; WAVE64-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; WAVE64-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; WAVE64-NEXT: [[V_CMP_CLASS_F16_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_CLASS_F16_e64 0, [[COPY]], [[COPY1]], implicit $exec
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; WAVE64-NEXT: S_ENDPGM 0, implicit [[V_CMP_CLASS_F16_e64_]]
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;
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; GFX11-TRUE16-LABEL: name: class_s16_vcc_vs
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; GFX11-TRUE16: liveins: $sgpr0, $vgpr0
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; GFX11-TRUE16-NEXT: {{ $}}
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; GFX11-TRUE16-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GFX11-TRUE16-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; GFX11-TRUE16-NEXT: [[COPY2:%[0-9]+]]:vgpr_16 = COPY [[COPY]].lo16
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; GFX11-TRUE16-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY1]]
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; GFX11-TRUE16-NEXT: [[COPY4:%[0-9]+]]:vgpr_16 = COPY [[COPY3]].lo16
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; GFX11-TRUE16-NEXT: [[V_CMP_CLASS_F16_t16_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_CLASS_F16_t16_e64 0, [[COPY2]], 0, [[COPY4]], 0, implicit $exec
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; GFX11-TRUE16-NEXT: S_ENDPGM 0, implicit [[V_CMP_CLASS_F16_t16_e64_]]
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;
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; GFX11-FAKE16-LABEL: name: class_s16_vcc_vs
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; GFX11-FAKE16: liveins: $sgpr0, $vgpr0
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; GFX11-FAKE16-NEXT: {{ $}}
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; GFX11-FAKE16-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GFX11-FAKE16-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; GFX11-FAKE16-NEXT: [[V_CMP_CLASS_F16_fake16_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_CLASS_F16_fake16_e64 0, [[COPY]], 0, [[COPY1]], implicit $exec
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; GFX11-FAKE16-NEXT: S_ENDPGM 0, implicit [[V_CMP_CLASS_F16_fake16_e64_]]
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;
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; GFX11-FOLD-TRUE16-LABEL: name: class_s16_vcc_vs
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; GFX11-FOLD-TRUE16: liveins: $sgpr0, $vgpr0
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; GFX11-FOLD-TRUE16-NEXT: {{ $}}
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; GFX11-FOLD-TRUE16-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GFX11-FOLD-TRUE16-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; GFX11-FOLD-TRUE16-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY1]]
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; GFX11-FOLD-TRUE16-NEXT: [[V_CMP_CLASS_F16_t16_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_CLASS_F16_t16_e64 0, [[COPY]].lo16, 0, [[COPY2]].lo16, 0, implicit $exec
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; GFX11-FOLD-TRUE16-NEXT: S_ENDPGM 0, implicit [[V_CMP_CLASS_F16_t16_e64_]]
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;
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; GFX11-FOLD-FAKE16-LABEL: name: class_s16_vcc_vs
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; GFX11-FOLD-FAKE16: liveins: $sgpr0, $vgpr0
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; GFX11-FOLD-FAKE16-NEXT: {{ $}}
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; GFX11-FOLD-FAKE16-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GFX11-FOLD-FAKE16-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; GFX11-FOLD-FAKE16-NEXT: [[V_CMP_CLASS_F16_fake16_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_CLASS_F16_fake16_e64 0, [[COPY]], 0, [[COPY1]], implicit $exec
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; GFX11-FOLD-FAKE16-NEXT: S_ENDPGM 0, implicit [[V_CMP_CLASS_F16_fake16_e64_]]
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;
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; SI-ERR-LABEL: name: class_s16_vcc_vs
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; SI-ERR: liveins: $sgpr0, $vgpr0
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; SI-ERR-NEXT: {{ $}}
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; SI-ERR-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
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; SI-ERR-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
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; SI-ERR-NEXT: [[TRUNC:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY]](s32)
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; SI-ERR-NEXT: [[INT:%[0-9]+]]:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), [[TRUNC]](s16), [[COPY1]](s32)
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; SI-ERR-NEXT: S_ENDPGM 0, implicit [[INT]](s1)
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%0:vgpr(s32) = COPY $vgpr0
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%1:sgpr(s32) = COPY $sgpr0
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%2:vgpr(s16) = G_TRUNC %0
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%4:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), %2, %1
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S_ENDPGM 0, implicit %4
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...
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---
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name: class_s16_vcc_vv
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1
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; WAVE32-LABEL: name: class_s16_vcc_vv
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; WAVE32: liveins: $vgpr0, $vgpr1
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; WAVE32-NEXT: {{ $}}
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; WAVE32-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; WAVE32-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; WAVE32-NEXT: [[V_CMP_CLASS_F16_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_CLASS_F16_e64 0, [[COPY]], [[COPY1]], implicit $exec
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; WAVE32-NEXT: S_ENDPGM 0, implicit [[V_CMP_CLASS_F16_e64_]]
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;
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; WAVE64-LABEL: name: class_s16_vcc_vv
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; WAVE64: liveins: $vgpr0, $vgpr1
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; WAVE64-NEXT: {{ $}}
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; WAVE64-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; WAVE64-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; WAVE64-NEXT: [[V_CMP_CLASS_F16_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_CLASS_F16_e64 0, [[COPY]], [[COPY1]], implicit $exec
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; WAVE64-NEXT: S_ENDPGM 0, implicit [[V_CMP_CLASS_F16_e64_]]
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;
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; GFX11-TRUE16-LABEL: name: class_s16_vcc_vv
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; GFX11-TRUE16: liveins: $vgpr0, $vgpr1
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; GFX11-TRUE16-NEXT: {{ $}}
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; GFX11-TRUE16-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GFX11-TRUE16-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; GFX11-TRUE16-NEXT: [[COPY2:%[0-9]+]]:vgpr_16 = COPY [[COPY]].lo16
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; GFX11-TRUE16-NEXT: [[COPY3:%[0-9]+]]:vgpr_16 = COPY [[COPY1]].lo16
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; GFX11-TRUE16-NEXT: [[V_CMP_CLASS_F16_t16_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_CLASS_F16_t16_e64 0, [[COPY2]], 0, [[COPY3]], 0, implicit $exec
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; GFX11-TRUE16-NEXT: S_ENDPGM 0, implicit [[V_CMP_CLASS_F16_t16_e64_]]
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;
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; GFX11-FAKE16-LABEL: name: class_s16_vcc_vv
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; GFX11-FAKE16: liveins: $vgpr0, $vgpr1
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; GFX11-FAKE16-NEXT: {{ $}}
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; GFX11-FAKE16-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GFX11-FAKE16-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; GFX11-FAKE16-NEXT: [[V_CMP_CLASS_F16_fake16_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_CLASS_F16_fake16_e64 0, [[COPY]], 0, [[COPY1]], implicit $exec
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; GFX11-FAKE16-NEXT: S_ENDPGM 0, implicit [[V_CMP_CLASS_F16_fake16_e64_]]
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;
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; GFX11-FOLD-TRUE16-LABEL: name: class_s16_vcc_vv
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; GFX11-FOLD-TRUE16: liveins: $vgpr0, $vgpr1
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; GFX11-FOLD-TRUE16-NEXT: {{ $}}
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; GFX11-FOLD-TRUE16-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GFX11-FOLD-TRUE16-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; GFX11-FOLD-TRUE16-NEXT: [[V_CMP_CLASS_F16_t16_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_CLASS_F16_t16_e64 0, [[COPY]].lo16, 0, [[COPY1]].lo16, 0, implicit $exec
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; GFX11-FOLD-TRUE16-NEXT: S_ENDPGM 0, implicit [[V_CMP_CLASS_F16_t16_e64_]]
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;
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; GFX11-FOLD-FAKE16-LABEL: name: class_s16_vcc_vv
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; GFX11-FOLD-FAKE16: liveins: $vgpr0, $vgpr1
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; GFX11-FOLD-FAKE16-NEXT: {{ $}}
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|
; GFX11-FOLD-FAKE16-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GFX11-FOLD-FAKE16-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
|
|
; GFX11-FOLD-FAKE16-NEXT: [[V_CMP_CLASS_F16_fake16_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_CLASS_F16_fake16_e64 0, [[COPY]], 0, [[COPY1]], implicit $exec
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; GFX11-FOLD-FAKE16-NEXT: S_ENDPGM 0, implicit [[V_CMP_CLASS_F16_fake16_e64_]]
|
|
;
|
|
; SI-ERR-LABEL: name: class_s16_vcc_vv
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|
; SI-ERR: liveins: $vgpr0, $vgpr1
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|
; SI-ERR-NEXT: {{ $}}
|
|
; SI-ERR-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
|
|
; SI-ERR-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
|
|
; SI-ERR-NEXT: [[TRUNC:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY]](s32)
|
|
; SI-ERR-NEXT: [[INT:%[0-9]+]]:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), [[TRUNC]](s16), [[COPY1]](s32)
|
|
; SI-ERR-NEXT: S_ENDPGM 0, implicit [[INT]](s1)
|
|
%0:vgpr(s32) = COPY $vgpr0
|
|
%1:vgpr(s32) = COPY $vgpr1
|
|
%2:vgpr(s16) = G_TRUNC %0
|
|
%4:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), %2, %1
|
|
S_ENDPGM 0, implicit %4
|
|
...
|