derek.holloway
7502bf64a4
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396 lines
13 KiB
YAML
396 lines
13 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=amdgcn -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=GCN,SI
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# RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=GCN,GFX10
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# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=GCN,GFX11-TRUE16
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# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=GCN,GFX11-FAKE16
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---
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name: anyext_sgpr_s16_to_sgpr_s32
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $sgpr0
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; GCN-LABEL: name: anyext_sgpr_s16_to_sgpr_s32
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; GCN: liveins: $sgpr0
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; GCN-NEXT: {{ $}}
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; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; GCN-NEXT: $sgpr0 = COPY [[COPY]]
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%0:sgpr(s32) = COPY $sgpr0
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%1:sgpr(s16) = G_TRUNC %0
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%2:sgpr(s32) = G_ANYEXT %1
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$sgpr0 = COPY %2
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...
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---
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name: anyext_sgpr_s32_to_sgpr_s64
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr0
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; GCN-LABEL: name: anyext_sgpr_s32_to_sgpr_s64
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; GCN: liveins: $sgpr0
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; GCN-NEXT: {{ $}}
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; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32_xexec_hi_and_sreg_32_xm0 = COPY $sgpr0
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; GCN-NEXT: [[DEF:%[0-9]+]]:sreg_32_xm0 = IMPLICIT_DEF
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; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[DEF]], %subreg.sub1
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; GCN-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
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%0:sgpr(s32) = COPY $sgpr0
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%1:sgpr(s64) = G_ANYEXT %0
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S_ENDPGM 0, implicit %1
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...
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---
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name: anyext_sgpr_s16_to_sgpr_s64
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $sgpr0
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; GCN-LABEL: name: anyext_sgpr_s16_to_sgpr_s64
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; GCN: liveins: $sgpr0
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; GCN-NEXT: {{ $}}
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; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; GCN-NEXT: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
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; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[DEF]], %subreg.sub1
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; GCN-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
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%0:sgpr(s32) = COPY $sgpr0
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%1:sgpr(s16) = G_TRUNC %0
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%2:sgpr(s64) = G_ANYEXT %1
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S_ENDPGM 0, implicit %2
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...
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---
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name: anyext_vgpr_s32_to_vgpr_s64
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0
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; GCN-LABEL: name: anyext_vgpr_s32_to_vgpr_s64
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; GCN: liveins: $vgpr0
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; GCN-NEXT: {{ $}}
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; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GCN-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
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; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[DEF]], %subreg.sub1
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; GCN-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
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%0:vgpr(s32) = COPY $vgpr0
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%1:vgpr(s64) = G_ANYEXT %0
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S_ENDPGM 0, implicit %1
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...
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---
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name: anyext_vgpr_s16_to_vgpr_s64
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $vgpr0
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; SI-LABEL: name: anyext_vgpr_s16_to_vgpr_s64
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; SI: liveins: $vgpr0
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; SI-NEXT: {{ $}}
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; SI-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; SI-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
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; SI-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[DEF]], %subreg.sub1
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; SI-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
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;
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; GFX10-LABEL: name: anyext_vgpr_s16_to_vgpr_s64
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; GFX10: liveins: $vgpr0
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; GFX10-NEXT: {{ $}}
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; GFX10-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GFX10-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
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; GFX10-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[V_MOV_B32_e32_]], %subreg.sub1
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; GFX10-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
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;
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; GFX11-TRUE16-LABEL: name: anyext_vgpr_s16_to_vgpr_s64
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; GFX11-TRUE16: liveins: $vgpr0
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; GFX11-TRUE16-NEXT: {{ $}}
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; GFX11-TRUE16-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GFX11-TRUE16-NEXT: [[COPY1:%[0-9]+]]:vgpr_16 = COPY [[COPY]].lo16
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; GFX11-TRUE16-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
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; GFX11-TRUE16-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY1]]
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; GFX11-TRUE16-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[V_MOV_B32_e32_]], %subreg.sub1
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; GFX11-TRUE16-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
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;
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; GFX11-FAKE16-LABEL: name: anyext_vgpr_s16_to_vgpr_s64
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; GFX11-FAKE16: liveins: $vgpr0
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; GFX11-FAKE16-NEXT: {{ $}}
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; GFX11-FAKE16-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GFX11-FAKE16-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
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; GFX11-FAKE16-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[V_MOV_B32_e32_]], %subreg.sub1
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; GFX11-FAKE16-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
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%0:vgpr(s32) = COPY $vgpr0
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%1:vgpr(s16) = G_TRUNC %0
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%2:vgpr(s64) = G_ANYEXT %1
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S_ENDPGM 0, implicit %2
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...
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# vcc is an invalid extension source
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# ---
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# name: anyext_vcc_s1_to_vgpr_s32
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# legalized: true
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# regBankSelected: true
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# body: |
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# bb.0:
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# liveins: $vgpr0
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# %0:vgpr(s32) = COPY $vgpr0
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# %1:vcc(s1) = G_ICMP intpred(eq), %0, %0
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# %2:vgpr(s32) = G_ANYEXT %1
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# $vgpr0 = COPY %2
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# ...
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---
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name: anyext_sgpr_s1_to_sgpr_s16
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $sgpr0
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; GCN-LABEL: name: anyext_sgpr_s1_to_sgpr_s16
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; GCN: liveins: $sgpr0
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; GCN-NEXT: {{ $}}
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; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; GCN-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 65535
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; GCN-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[S_MOV_B32_]], [[COPY]], implicit-def dead $scc
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; GCN-NEXT: $sgpr0 = COPY [[S_AND_B32_]]
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%0:sgpr(s32) = COPY $sgpr0
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%1:sgpr(s1) = G_TRUNC %0
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%2:sgpr(s16) = G_ANYEXT %1
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%3:sgpr(s32) = G_ZEXT %2
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$sgpr0 = COPY %3
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...
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---
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name: anyext_sgpr_s1_to_sgpr_s32
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $sgpr0
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; GCN-LABEL: name: anyext_sgpr_s1_to_sgpr_s32
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; GCN: liveins: $sgpr0
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; GCN-NEXT: {{ $}}
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; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; GCN-NEXT: $sgpr0 = COPY [[COPY]]
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%0:sgpr(s32) = COPY $sgpr0
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%1:sgpr(s1) = G_TRUNC %0
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%2:sgpr(s32) = G_ANYEXT %1
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$sgpr0 = COPY %2
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...
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---
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name: anyext_sgpr_s1_to_sgpr_s64
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $sgpr0
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; GCN-LABEL: name: anyext_sgpr_s1_to_sgpr_s64
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; GCN: liveins: $sgpr0
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; GCN-NEXT: {{ $}}
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; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; GCN-NEXT: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
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; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[DEF]], %subreg.sub1
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; GCN-NEXT: $sgpr0_sgpr1 = COPY [[REG_SEQUENCE]]
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%0:sgpr(s32) = COPY $sgpr0
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%1:sgpr(s1) = G_TRUNC %0
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%2:sgpr(s64) = G_ANYEXT %1
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$sgpr0_sgpr1 = COPY %2
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...
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---
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name: anyext_vgpr_s1_to_vgpr_s16
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $vgpr0
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; SI-LABEL: name: anyext_vgpr_s1_to_vgpr_s16
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; SI: liveins: $vgpr0
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; SI-NEXT: {{ $}}
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; SI-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; SI-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 65535
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; SI-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[S_MOV_B32_]], [[COPY]], implicit $exec
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; SI-NEXT: $vgpr0 = COPY [[V_AND_B32_e64_]]
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;
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; GFX10-LABEL: name: anyext_vgpr_s1_to_vgpr_s16
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; GFX10: liveins: $vgpr0
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; GFX10-NEXT: {{ $}}
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; GFX10-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GFX10-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 65535
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; GFX10-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[S_MOV_B32_]], [[COPY]], implicit $exec
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; GFX10-NEXT: $vgpr0 = COPY [[V_AND_B32_e64_]]
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;
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; GFX11-TRUE16-LABEL: name: anyext_vgpr_s1_to_vgpr_s16
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; GFX11-TRUE16: liveins: $vgpr0
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; GFX11-TRUE16-NEXT: {{ $}}
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; GFX11-TRUE16-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GFX11-TRUE16-NEXT: [[COPY1:%[0-9]+]]:vgpr_16 = COPY [[COPY]].lo16
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; GFX11-TRUE16-NEXT: [[V_MOV_B16_t16_e64_:%[0-9]+]]:vgpr_16 = V_MOV_B16_t16_e64 0, 0, 0, implicit $exec
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; GFX11-TRUE16-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vgpr_32 = REG_SEQUENCE [[COPY1]], %subreg.lo16, [[V_MOV_B16_t16_e64_]], %subreg.hi16
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; GFX11-TRUE16-NEXT: $vgpr0 = COPY [[REG_SEQUENCE]]
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;
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; GFX11-FAKE16-LABEL: name: anyext_vgpr_s1_to_vgpr_s16
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; GFX11-FAKE16: liveins: $vgpr0
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; GFX11-FAKE16-NEXT: {{ $}}
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; GFX11-FAKE16-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GFX11-FAKE16-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 65535
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; GFX11-FAKE16-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[S_MOV_B32_]], [[COPY]], implicit $exec
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; GFX11-FAKE16-NEXT: $vgpr0 = COPY [[V_AND_B32_e64_]]
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%0:vgpr(s32) = COPY $vgpr0
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%1:vgpr(s1) = G_TRUNC %0
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%2:vgpr(s16) = G_ANYEXT %1
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%3:vgpr(s32) = G_ZEXT %2
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$vgpr0 = COPY %3
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...
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---
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name: anyext_vgpr_s1_to_vgpr_s32
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $vgpr0
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; SI-LABEL: name: anyext_vgpr_s1_to_vgpr_s32
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; SI: liveins: $vgpr0
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; SI-NEXT: {{ $}}
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; SI-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; SI-NEXT: $vgpr0 = COPY [[COPY]]
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;
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; GFX10-LABEL: name: anyext_vgpr_s1_to_vgpr_s32
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; GFX10: liveins: $vgpr0
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; GFX10-NEXT: {{ $}}
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; GFX10-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GFX10-NEXT: $vgpr0 = COPY [[COPY]]
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;
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; GFX11-TRUE16-LABEL: name: anyext_vgpr_s1_to_vgpr_s32
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; GFX11-TRUE16: liveins: $vgpr0
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; GFX11-TRUE16-NEXT: {{ $}}
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; GFX11-TRUE16-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GFX11-TRUE16-NEXT: [[COPY1:%[0-9]+]]:vgpr_16 = COPY [[COPY]].lo16
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; GFX11-TRUE16-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY1]]
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; GFX11-TRUE16-NEXT: $vgpr0 = COPY [[COPY2]]
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;
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; GFX11-FAKE16-LABEL: name: anyext_vgpr_s1_to_vgpr_s32
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; GFX11-FAKE16: liveins: $vgpr0
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; GFX11-FAKE16-NEXT: {{ $}}
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; GFX11-FAKE16-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GFX11-FAKE16-NEXT: $vgpr0 = COPY [[COPY]]
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%0:vgpr(s32) = COPY $vgpr0
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%1:vgpr(s1) = G_TRUNC %0
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%2:vgpr(s32) = G_ANYEXT %1
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$vgpr0 = COPY %2
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...
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---
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name: anyext_sgpr_s1_to_vgpr_s32
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $sgpr0
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; GCN-LABEL: name: anyext_sgpr_s1_to_vgpr_s32
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; GCN: liveins: $sgpr0
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; GCN-NEXT: {{ $}}
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; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
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; GCN-NEXT: $sgpr0 = COPY [[COPY]]
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%0:sgpr(s32) = COPY $sgpr0
|
|
%1:sgpr(s1) = G_TRUNC %0
|
|
%2:sgpr(s32) = G_ANYEXT %1
|
|
$sgpr0 = COPY %2
|
|
...
|
|
|
|
---
|
|
|
|
name: anyext_vgpr_s16_to_vgpr_s32
|
|
legalized: true
|
|
regBankSelected: true
|
|
body: |
|
|
bb.0:
|
|
liveins: $vgpr0
|
|
|
|
; SI-LABEL: name: anyext_vgpr_s16_to_vgpr_s32
|
|
; SI: liveins: $vgpr0
|
|
; SI-NEXT: {{ $}}
|
|
; SI-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
|
; SI-NEXT: $vgpr0 = COPY [[COPY]]
|
|
;
|
|
; GFX10-LABEL: name: anyext_vgpr_s16_to_vgpr_s32
|
|
; GFX10: liveins: $vgpr0
|
|
; GFX10-NEXT: {{ $}}
|
|
; GFX10-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
|
; GFX10-NEXT: $vgpr0 = COPY [[COPY]]
|
|
;
|
|
; GFX11-TRUE16-LABEL: name: anyext_vgpr_s16_to_vgpr_s32
|
|
; GFX11-TRUE16: liveins: $vgpr0
|
|
; GFX11-TRUE16-NEXT: {{ $}}
|
|
; GFX11-TRUE16-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
|
; GFX11-TRUE16-NEXT: [[COPY1:%[0-9]+]]:vgpr_16 = COPY [[COPY]].lo16
|
|
; GFX11-TRUE16-NEXT: [[DEF:%[0-9]+]]:vgpr_16 = IMPLICIT_DEF
|
|
; GFX11-TRUE16-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vgpr_32 = REG_SEQUENCE [[COPY1]], %subreg.lo16, [[DEF]], %subreg.hi16
|
|
; GFX11-TRUE16-NEXT: $vgpr0 = COPY [[REG_SEQUENCE]]
|
|
;
|
|
; GFX11-FAKE16-LABEL: name: anyext_vgpr_s16_to_vgpr_s32
|
|
; GFX11-FAKE16: liveins: $vgpr0
|
|
; GFX11-FAKE16-NEXT: {{ $}}
|
|
; GFX11-FAKE16-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
|
; GFX11-FAKE16-NEXT: $vgpr0 = COPY [[COPY]]
|
|
%0:vgpr(s32) = COPY $vgpr0
|
|
%1:vgpr(s16) = G_TRUNC %0
|
|
%2:vgpr(s32) = G_ANYEXT %1
|
|
$vgpr0 = COPY %2
|
|
|
|
...
|
|
|
|
# The source register already has an assigned register class that
|
|
# should not be interpreted as vcc.
|
|
---
|
|
|
|
name: anyext_regclass_sgpr_s1_to_sgpr_s32
|
|
legalized: true
|
|
regBankSelected: true
|
|
body: |
|
|
bb.0:
|
|
liveins: $sgpr0
|
|
|
|
; GCN-LABEL: name: anyext_regclass_sgpr_s1_to_sgpr_s32
|
|
; GCN: liveins: $sgpr0
|
|
; GCN-NEXT: {{ $}}
|
|
; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
|
|
; GCN-NEXT: $sgpr0 = COPY [[COPY]]
|
|
%0:sgpr(s32) = COPY $sgpr0
|
|
%1:sreg_32(s1) = G_TRUNC %0
|
|
%2:sgpr(s32) = G_ANYEXT %1
|
|
$sgpr0 = COPY %2
|
|
...
|