TheRock/compiler/amd-llvm/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-build-vector.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs  -o - %s | FileCheck -check-prefix=GCN  %s

---
name: test_build_vector_v_v2s32_v_s32_v_s32
legalized:       true
regBankSelected: true
tracksRegLiveness: true

body: |
  bb.0:
    liveins: $vgpr0, $vgpr1

    ; GCN-LABEL: name: test_build_vector_v_v2s32_v_s32_v_s32
    ; GCN: liveins: $vgpr0, $vgpr1
    ; GCN-NEXT: {{  $}}
    ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
    ; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1
    ; GCN-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
    %0:vgpr(s32) = COPY $vgpr0
    %1:vgpr(s32) = COPY $vgpr1
    %2:vgpr(<2 x s32>) = G_BUILD_VECTOR %0, %1
    S_ENDPGM 0, implicit %2
...

---
name: test_build_vector_v_v2s32_s_s32_v_s32
legalized:       true
regBankSelected: true
tracksRegLiveness: true

body: |
  bb.0:
    liveins: $sgpr0, $vgpr0

    ; GCN-LABEL: name: test_build_vector_v_v2s32_s_s32_v_s32
    ; GCN: liveins: $sgpr0, $vgpr0
    ; GCN-NEXT: {{  $}}
    ; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
    ; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1
    ; GCN-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
    %0:sgpr(s32) = COPY $sgpr0
    %1:vgpr(s32) = COPY $vgpr0
    %2:vgpr(<2 x s32>) = G_BUILD_VECTOR %0, %1
    S_ENDPGM 0, implicit %2
...

---
name: test_build_vector_v_v2s32_v_s32_s_s32
legalized:       true
regBankSelected: true
tracksRegLiveness: true

body: |
  bb.0:
    liveins: $sgpr0, $vgpr0

    ; GCN-LABEL: name: test_build_vector_v_v2s32_v_s32_s_s32
    ; GCN: liveins: $sgpr0, $vgpr0
    ; GCN-NEXT: {{  $}}
    ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GCN-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
    ; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1
    ; GCN-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
    %0:vgpr(s32) = COPY $vgpr0
    %1:sgpr(s32) = COPY $sgpr0
    %2:vgpr(<2 x s32>) = G_BUILD_VECTOR %0, %1
    S_ENDPGM 0, implicit %2
...

---
name: test_build_vector_s_v2s32_s_s32_s_s32
legalized:       true
regBankSelected: true
tracksRegLiveness: true

body: |
  bb.0:
    liveins: $sgpr0, $sgpr1

    ; GCN-LABEL: name: test_build_vector_s_v2s32_s_s32_s_s32
    ; GCN: liveins: $sgpr0, $sgpr1
    ; GCN-NEXT: {{  $}}
    ; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
    ; GCN-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
    ; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1
    ; GCN-NEXT: S_ENDPGM 0, implicit [[REG_SEQUENCE]]
    %0:sgpr(s32) = COPY $sgpr0
    %1:sgpr(s32) = COPY $sgpr1
    %2:sgpr(<2 x s32>) = G_BUILD_VECTOR %0, %1
    S_ENDPGM 0, implicit %2
...

---
name: test_build_vector_s_v2s64_s_s64_s_s64
legalized:       true
regBankSelected: true
tracksRegLiveness: true

body: |
  bb.0:
    liveins: $sgpr0_sgpr1, $sgpr2_sgpr3

    ; GCN-LABEL: name: test_build_vector_s_v2s64_s_s64_s_s64
    ; GCN: liveins: $sgpr0_sgpr1, $sgpr2_sgpr3
    ; GCN-NEXT: {{  $}}
    ; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
    ; GCN-NEXT: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr2_sgpr3
    ; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0_sub1, [[COPY1]], %subreg.sub2_sub3
    ; GCN-NEXT: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[REG_SEQUENCE]]
    %0:sgpr(s64) = COPY $sgpr0_sgpr1
    %1:sgpr(s64) = COPY $sgpr2_sgpr3
    %4:sgpr(<2 x s64>) = G_BUILD_VECTOR %0, %1
    $sgpr0_sgpr1_sgpr2_sgpr3 = COPY %4
...