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57 lines
2.3 KiB
LLVM
57 lines
2.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx700 < %s | FileCheck -check-prefixes=GFX7 %s
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; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx803 < %s | FileCheck -check-prefixes=GFX8 %s
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; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck -check-prefixes=GFX11 %s
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define amdgpu_kernel void @fcmp_uniform_select(float %a, i32 %b, i32 %c, ptr addrspace(1) %out) {
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; GFX7-LABEL: fcmp_uniform_select:
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; GFX7: ; %bb.0:
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; GFX7-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x9
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; GFX7-NEXT: s_load_dword s3, s[4:5], 0xb
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; GFX7-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0xd
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; GFX7-NEXT: s_mov_b32 s2, -1
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; GFX7-NEXT: s_waitcnt lgkmcnt(0)
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; GFX7-NEXT: v_cmp_eq_f32_e64 s[4:5], s6, 0
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; GFX7-NEXT: s_or_b64 s[4:5], s[4:5], s[4:5]
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; GFX7-NEXT: s_cselect_b32 s3, s7, s3
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; GFX7-NEXT: v_mov_b32_e32 v0, s3
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; GFX7-NEXT: s_mov_b32 s3, 0xf000
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; GFX7-NEXT: buffer_store_dword v0, off, s[0:3], 0
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; GFX7-NEXT: s_endpgm
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;
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; GFX8-LABEL: fcmp_uniform_select:
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; GFX8: ; %bb.0:
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; GFX8-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
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; GFX8-NEXT: s_load_dword s6, s[4:5], 0x2c
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; GFX8-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x34
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; GFX8-NEXT: s_waitcnt lgkmcnt(0)
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; GFX8-NEXT: v_cmp_eq_f32_e64 s[4:5], s0, 0
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; GFX8-NEXT: s_cmp_lg_u64 s[4:5], 0
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; GFX8-NEXT: s_cselect_b32 s0, s1, s6
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; GFX8-NEXT: v_mov_b32_e32 v0, s2
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; GFX8-NEXT: v_mov_b32_e32 v2, s0
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; GFX8-NEXT: v_mov_b32_e32 v1, s3
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; GFX8-NEXT: flat_store_dword v[0:1], v2
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; GFX8-NEXT: s_endpgm
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;
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; GFX11-LABEL: fcmp_uniform_select:
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; GFX11: ; %bb.0:
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; GFX11-NEXT: s_clause 0x2
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; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
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; GFX11-NEXT: s_load_b32 s6, s[4:5], 0x2c
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; GFX11-NEXT: s_load_b64 s[2:3], s[4:5], 0x34
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; GFX11-NEXT: v_mov_b32_e32 v1, 0
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; GFX11-NEXT: s_waitcnt lgkmcnt(0)
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; GFX11-NEXT: v_cmp_eq_f32_e64 s0, s0, 0
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; GFX11-NEXT: s_cmp_lg_u32 s0, 0
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; GFX11-NEXT: s_cselect_b32 s0, s1, s6
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; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
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; GFX11-NEXT: v_mov_b32_e32 v0, s0
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; GFX11-NEXT: global_store_b32 v1, v0, s[2:3]
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; GFX11-NEXT: s_endpgm
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%cmp = fcmp oeq float %a, 0.0
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%sel = select i1 %cmp, i32 %b, i32 %c
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store i32 %sel, ptr addrspace(1) %out
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ret void
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}
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