derek.holloway
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112 lines
5.7 KiB
YAML
112 lines
5.7 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -run-pass=instruction-select -global-isel-abort=0 -verify-machineinstrs -o - %s | FileCheck -check-prefixes=GCN,GFX9GFX10 %s
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# RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -run-pass=instruction-select -global-isel-abort=0 -verify-machineinstrs -o - %s | FileCheck -check-prefixes=GCN,GFX9GFX10 %s
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# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 -run-pass=instruction-select -global-isel-abort=0 -verify-machineinstrs -o - %s | FileCheck -check-prefixes=GCN,GFX11-TRUE16 %s
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# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 -run-pass=instruction-select -global-isel-abort=0 -verify-machineinstrs -o - %s | FileCheck -check-prefixes=GCN,GFX11-FAKE16 %s
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---
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name: fmul_v2f16_vv
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1
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; GCN-LABEL: name: fmul_v2f16_vv
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; GCN: liveins: $vgpr0, $vgpr1
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; GCN-NEXT: {{ $}}
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; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; GCN-NEXT: [[V_PK_MUL_F16_:%[0-9]+]]:vgpr_32 = nofpexcept V_PK_MUL_F16 8, [[COPY]], 8, [[COPY1]], 0, 0, 0, 0, 0, implicit $mode, implicit $exec
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; GCN-NEXT: S_ENDPGM 0, implicit [[V_PK_MUL_F16_]]
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%0:vgpr(<2 x s16>) = COPY $vgpr0
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%1:vgpr(<2 x s16>) = COPY $vgpr1
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%2:vgpr(<2 x s16>) = G_FMUL %0, %1
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S_ENDPGM 0, implicit %2
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...
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---
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name: fmul_v2f16_fneg_v_fneg_v
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1
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; GCN-LABEL: name: fmul_v2f16_fneg_v_fneg_v
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; GCN: liveins: $vgpr0, $vgpr1
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; GCN-NEXT: {{ $}}
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; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; GCN-NEXT: [[V_PK_MUL_F16_:%[0-9]+]]:vgpr_32 = nofpexcept V_PK_MUL_F16 11, [[COPY]], 11, [[COPY1]], 0, 0, 0, 0, 0, implicit $mode, implicit $exec
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; GCN-NEXT: S_ENDPGM 0, implicit [[V_PK_MUL_F16_]]
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%0:vgpr(<2 x s16>) = COPY $vgpr0
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%1:vgpr(<2 x s16>) = COPY $vgpr1
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%2:vgpr(<2 x s16>) = G_FNEG %0
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%3:vgpr(<2 x s16>) = G_FNEG %1
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%4:vgpr(<2 x s16>) = G_FMUL %2, %3
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S_ENDPGM 0, implicit %4
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...
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---
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name: fmul_v2f16_fneg_lo_v_v
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1, $vgpr2
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; GFX9GFX10-LABEL: name: fmul_v2f16_fneg_lo_v_v
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; GFX9GFX10: liveins: $vgpr0, $vgpr1, $vgpr2
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; GFX9GFX10-NEXT: {{ $}}
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; GFX9GFX10-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GFX9GFX10-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; GFX9GFX10-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
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; GFX9GFX10-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 32768
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; GFX9GFX10-NEXT: [[V_XOR_B32_e64_:%[0-9]+]]:vgpr_32 = V_XOR_B32_e64 [[S_MOV_B32_]], [[COPY1]], implicit $exec
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; GFX9GFX10-NEXT: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 65535, [[V_XOR_B32_e64_]], implicit $exec
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; GFX9GFX10-NEXT: [[V_LSHL_OR_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHL_OR_B32_e64 [[COPY2]], 16, [[V_AND_B32_e32_]], implicit $exec
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; GFX9GFX10-NEXT: [[V_PK_MUL_F16_:%[0-9]+]]:vgpr_32 = nofpexcept V_PK_MUL_F16 8, [[V_LSHL_OR_B32_e64_]], 8, [[COPY]], 0, 0, 0, 0, 0, implicit $mode, implicit $exec
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; GFX9GFX10-NEXT: S_ENDPGM 0, implicit [[V_PK_MUL_F16_]]
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;
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; GFX11-TRUE16-LABEL: name: fmul_v2f16_fneg_lo_v_v
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; GFX11-TRUE16: liveins: $vgpr0, $vgpr1, $vgpr2
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; GFX11-TRUE16-NEXT: {{ $}}
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; GFX11-TRUE16-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GFX11-TRUE16-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; GFX11-TRUE16-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
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; GFX11-TRUE16-NEXT: [[COPY3:%[0-9]+]]:vgpr_16 = COPY [[COPY1]].lo16
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; GFX11-TRUE16-NEXT: [[V_XOR_B16_t16_e64_:%[0-9]+]]:vgpr_16 = V_XOR_B16_t16_e64 0, 32768, 0, [[COPY3]], 0, implicit $exec
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; GFX11-TRUE16-NEXT: [[DEF:%[0-9]+]]:vgpr_16 = IMPLICIT_DEF
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; GFX11-TRUE16-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vgpr_32 = REG_SEQUENCE [[V_XOR_B16_t16_e64_]], %subreg.lo16, [[DEF]], %subreg.hi16
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; GFX11-TRUE16-NEXT: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 65535, [[REG_SEQUENCE]], implicit $exec
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; GFX11-TRUE16-NEXT: [[V_LSHL_OR_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHL_OR_B32_e64 [[COPY2]], 16, [[V_AND_B32_e32_]], implicit $exec
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; GFX11-TRUE16-NEXT: [[V_PK_MUL_F16_:%[0-9]+]]:vgpr_32 = nofpexcept V_PK_MUL_F16 8, [[V_LSHL_OR_B32_e64_]], 8, [[COPY]], 0, 0, 0, 0, 0, implicit $mode, implicit $exec
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; GFX11-TRUE16-NEXT: S_ENDPGM 0, implicit [[V_PK_MUL_F16_]]
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;
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; GFX11-FAKE16-LABEL: name: fmul_v2f16_fneg_lo_v_v
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; GFX11-FAKE16: liveins: $vgpr0, $vgpr1, $vgpr2
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; GFX11-FAKE16-NEXT: {{ $}}
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; GFX11-FAKE16-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GFX11-FAKE16-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; GFX11-FAKE16-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
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; GFX11-FAKE16-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 32768
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; GFX11-FAKE16-NEXT: [[V_XOR_B32_e64_:%[0-9]+]]:vgpr_32 = V_XOR_B32_e64 [[S_MOV_B32_]], [[COPY1]], implicit $exec
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; GFX11-FAKE16-NEXT: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 65535, [[V_XOR_B32_e64_]], implicit $exec
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; GFX11-FAKE16-NEXT: [[V_LSHL_OR_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHL_OR_B32_e64 [[COPY2]], 16, [[V_AND_B32_e32_]], implicit $exec
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; GFX11-FAKE16-NEXT: [[V_PK_MUL_F16_:%[0-9]+]]:vgpr_32 = nofpexcept V_PK_MUL_F16 8, [[V_LSHL_OR_B32_e64_]], 8, [[COPY]], 0, 0, 0, 0, 0, implicit $mode, implicit $exec
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; GFX11-FAKE16-NEXT: S_ENDPGM 0, implicit [[V_PK_MUL_F16_]]
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%0:vgpr(<2 x s16>) = COPY $vgpr0
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%1:vgpr(s32) = COPY $vgpr1
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%2:vgpr(s32) = COPY $vgpr2
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%3:vgpr(s16) = G_TRUNC %1
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%4:vgpr(s16) = G_FNEG %3
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%5:vgpr(s32) = G_ANYEXT %4
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%6:vgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %5, %2
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%7:vgpr(<2 x s16>) = G_FMUL %6, %0
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S_ENDPGM 0, implicit %7
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...
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