derek.holloway
7502bf64a4
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94 lines
3.4 KiB
LLVM
94 lines
3.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
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; RUN: llc -mtriple=amdgcn -mcpu=gfx1030 -global-isel < %s | FileCheck %s
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; early-tailduplication deletes cycle exit block created by structurize-cfg
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; that had exactly one predecessor. Now, new cycle exit block has two
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; predecessors, we need to find predecessor that belongs to the cycle.
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define amdgpu_ps void @_amdgpu_ps_main(i1 %arg) {
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; CHECK-LABEL: _amdgpu_ps_main:
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; CHECK: ; %bb.0: ; %bb
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; CHECK-NEXT: s_mov_b32 s4, 0
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; CHECK-NEXT: v_and_b32_e32 v0, 1, v0
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; CHECK-NEXT: s_mov_b32 s5, s4
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; CHECK-NEXT: s_mov_b32 s6, s4
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; CHECK-NEXT: s_mov_b32 s7, s4
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; CHECK-NEXT: s_mov_b32 s8, SCRATCH_RSRC_DWORD0
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; CHECK-NEXT: s_buffer_load_dword s1, s[4:7], 0x0
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; CHECK-NEXT: s_mov_b32 s9, SCRATCH_RSRC_DWORD1
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; CHECK-NEXT: s_mov_b32 s10, -1
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; CHECK-NEXT: s_mov_b32 s11, 0x31c16000
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; CHECK-NEXT: s_add_u32 s8, s8, s0
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; CHECK-NEXT: v_cmp_ne_u32_e64 s0, 0, v0
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; CHECK-NEXT: s_addc_u32 s9, s9, 0
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; CHECK-NEXT: s_mov_b32 s32, 0
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; CHECK-NEXT: s_waitcnt lgkmcnt(0)
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; CHECK-NEXT: s_cmp_ge_i32 s1, 0
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; CHECK-NEXT: s_cbranch_scc0 .LBB0_2
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; CHECK-NEXT: .LBB0_1: ; %bb12
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; CHECK-NEXT: v_cndmask_b32_e64 v0, 1.0, 0, s4
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; CHECK-NEXT: v_mov_b32_e32 v1, 0
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; CHECK-NEXT: v_mov_b32_e32 v2, 0
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; CHECK-NEXT: v_mov_b32_e32 v3, 0
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; CHECK-NEXT: v_mov_b32_e32 v4, 0
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; CHECK-NEXT: s_mov_b64 s[0:1], s[8:9]
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; CHECK-NEXT: s_mov_b64 s[2:3], s[10:11]
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; CHECK-NEXT: s_swappc_b64 s[30:31], 0
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; CHECK-NEXT: .LBB0_2: ; %bb2.preheader
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; CHECK-NEXT: s_mov_b32 s1, 0
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; CHECK-NEXT: v_mov_b32_e32 v0, s1
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; CHECK-NEXT: s_branch .LBB0_4
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; CHECK-NEXT: .p2align 6
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; CHECK-NEXT: .LBB0_3: ; %bb6
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; CHECK-NEXT: ; in Loop: Header=BB0_4 Depth=1
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; CHECK-NEXT: s_or_b32 exec_lo, exec_lo, s3
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; CHECK-NEXT: s_and_b32 s2, 1, s2
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; CHECK-NEXT: v_or_b32_e32 v1, 1, v0
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; CHECK-NEXT: v_cmp_ne_u32_e64 s2, 0, s2
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; CHECK-NEXT: v_cmp_gt_i32_e32 vcc_lo, 0, v0
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; CHECK-NEXT: v_mov_b32_e32 v0, v1
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; CHECK-NEXT: s_and_b32 s4, s2, s1
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; CHECK-NEXT: s_andn2_b32 s1, s1, exec_lo
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; CHECK-NEXT: s_and_b32 s2, exec_lo, s4
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; CHECK-NEXT: s_or_b32 s1, s1, s2
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; CHECK-NEXT: s_cbranch_vccz .LBB0_1
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; CHECK-NEXT: .LBB0_4: ; %bb2
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; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: s_mov_b32 s2, 0
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; CHECK-NEXT: s_and_saveexec_b32 s3, s0
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; CHECK-NEXT: s_cbranch_execz .LBB0_3
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; CHECK-NEXT: ; %bb.5: ; %bb5
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; CHECK-NEXT: ; in Loop: Header=BB0_4 Depth=1
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; CHECK-NEXT: s_mov_b32 s2, 1
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; CHECK-NEXT: s_branch .LBB0_3
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bb:
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%i = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> zeroinitializer, i32 0, i32 0)
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%i1 = icmp slt i32 %i, 0
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br i1 %i1, label %bb2, label %bb12
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bb2:
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%i3 = phi i1 [ %i9, %bb6 ], [ false, %bb ]
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%i4 = phi i32 [ %i10, %bb6 ], [ 0, %bb ]
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br i1 %arg, label %bb5, label %bb6
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bb5:
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br label %bb6
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bb6:
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%i7 = phi i32 [ 0, %bb2 ], [ 1, %bb5 ]
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%i8 = icmp ne i32 %i7, 0
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%i9 = select i1 %i8, i1 %i3, i1 false
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%i10 = or i32 %i4, 1
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%i11 = icmp slt i32 %i4, 0
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br i1 %i11, label %bb2, label %bb12
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bb12:
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%i13 = phi i1 [ false, %bb ], [ %i9, %bb6 ]
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%i14 = select i1 %i13, float 0.000000e+00, float 1.000000e+00
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%i15 = insertelement <4 x float> zeroinitializer, float %i14, i64 0
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call amdgpu_gfx addrspace(4) void null(<4 x float> %i15, i32 0)
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unreachable
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}
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declare i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32>, i32, i32 immarg)
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