derek.holloway
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124 lines
4.9 KiB
YAML
124 lines
4.9 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -O0 -run-pass=legalizer %s -o - | FileCheck %s
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# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=legalizer %s -o - | FileCheck %s
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---
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name: atomic_cmpxchg_local_i32
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body: |
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bb.0:
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liveins: $sgpr0, $sgpr1, $sgpr2
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; CHECK-LABEL: name: atomic_cmpxchg_local_i32
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; CHECK: liveins: $sgpr0, $sgpr1, $sgpr2
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $sgpr0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr1
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr2
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; CHECK-NEXT: [[ATOMIC_CMPXCHG:%[0-9]+]]:_(s32) = G_ATOMIC_CMPXCHG [[COPY]](p3), [[COPY1]], [[COPY2]] :: (load store seq_cst (s32), addrspace 3)
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%0:_(p3) = COPY $sgpr0
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%1:_(s32) = COPY $sgpr1
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%2:_(s32) = COPY $sgpr2
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%3:_(s32) = G_ATOMIC_CMPXCHG %0, %1, %2 :: (load store seq_cst (s32), addrspace 3)
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...
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---
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name: atomic_cmpxchg_local_i64
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body: |
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bb.0:
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liveins: $sgpr0, $sgpr1, $sgpr2
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; CHECK-LABEL: name: atomic_cmpxchg_local_i64
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; CHECK: liveins: $sgpr0, $sgpr1, $sgpr2
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $sgpr0
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr1
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr2
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; CHECK-NEXT: [[ATOMIC_CMPXCHG:%[0-9]+]]:_(s32) = G_ATOMIC_CMPXCHG [[COPY]](p3), [[COPY1]], [[COPY2]] :: (load store seq_cst (s64), addrspace 3)
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%0:_(p3) = COPY $sgpr0
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%1:_(s32) = COPY $sgpr1
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%2:_(s32) = COPY $sgpr2
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%3:_(s32) = G_ATOMIC_CMPXCHG %0, %1, %2 :: (load store seq_cst (s64), addrspace 3)
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...
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---
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name: atomic_cmpxchg_global_i32
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body: |
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bb.0:
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liveins: $sgpr0_sgpr1, $sgpr2, $sgpr3
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; CHECK-LABEL: name: atomic_cmpxchg_global_i32
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; CHECK: liveins: $sgpr0_sgpr1, $sgpr2, $sgpr3
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $sgpr0_sgpr1
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr2
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr3
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; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY2]](s32), [[COPY1]](s32)
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; CHECK-NEXT: [[AMDGPU_ATOMIC_CMPXCHG:%[0-9]+]]:_(s32) = G_AMDGPU_ATOMIC_CMPXCHG [[COPY]](p1), [[BUILD_VECTOR]] :: (load store seq_cst (s32), addrspace 1)
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%0:_(p1) = COPY $sgpr0_sgpr1
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%1:_(s32) = COPY $sgpr2
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%2:_(s32) = COPY $sgpr3
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%3:_(s32) = G_ATOMIC_CMPXCHG %0, %1, %2 :: (load store seq_cst (s32), addrspace 1)
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...
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---
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name: atomic_cmpxchg_global_i64
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body: |
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bb.0:
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liveins: $sgpr0_sgpr1, $sgpr2, $sgpr3
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; CHECK-LABEL: name: atomic_cmpxchg_global_i64
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; CHECK: liveins: $sgpr0_sgpr1, $sgpr2, $sgpr3
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $sgpr0_sgpr1
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr2
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr3
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; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY2]](s32), [[COPY1]](s32)
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; CHECK-NEXT: [[AMDGPU_ATOMIC_CMPXCHG:%[0-9]+]]:_(s32) = G_AMDGPU_ATOMIC_CMPXCHG [[COPY]](p1), [[BUILD_VECTOR]] :: (load store seq_cst (s64), addrspace 1)
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%0:_(p1) = COPY $sgpr0_sgpr1
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%1:_(s32) = COPY $sgpr2
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%2:_(s32) = COPY $sgpr3
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%3:_(s32) = G_ATOMIC_CMPXCHG %0, %1, %2 :: (load store seq_cst (s64), addrspace 1)
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...
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---
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name: atomic_cmpxchg_flat_i32
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body: |
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bb.0:
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liveins: $sgpr0_sgpr1, $sgpr2, $sgpr3
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; CHECK-LABEL: name: atomic_cmpxchg_flat_i32
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; CHECK: liveins: $sgpr0_sgpr1, $sgpr2, $sgpr3
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $sgpr0_sgpr1
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr2
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr3
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; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY2]](s32), [[COPY1]](s32)
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; CHECK-NEXT: [[AMDGPU_ATOMIC_CMPXCHG:%[0-9]+]]:_(s32) = G_AMDGPU_ATOMIC_CMPXCHG [[COPY]](p0), [[BUILD_VECTOR]] :: (load store seq_cst (s32))
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%0:_(p0) = COPY $sgpr0_sgpr1
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%1:_(s32) = COPY $sgpr2
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%2:_(s32) = COPY $sgpr3
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%3:_(s32) = G_ATOMIC_CMPXCHG %0, %1, %2 :: (load store seq_cst (s32), addrspace 0)
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...
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---
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name: atomic_cmpxchg_flat_i64
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body: |
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bb.0:
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liveins: $sgpr0_sgpr1, $sgpr2, $sgpr3
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; CHECK-LABEL: name: atomic_cmpxchg_flat_i64
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; CHECK: liveins: $sgpr0_sgpr1, $sgpr2, $sgpr3
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; CHECK-NEXT: {{ $}}
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; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $sgpr0_sgpr1
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; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $sgpr2
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; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $sgpr3
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; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY2]](s32), [[COPY1]](s32)
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; CHECK-NEXT: [[AMDGPU_ATOMIC_CMPXCHG:%[0-9]+]]:_(s32) = G_AMDGPU_ATOMIC_CMPXCHG [[COPY]](p0), [[BUILD_VECTOR]] :: (load store seq_cst (s64))
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%0:_(p0) = COPY $sgpr0_sgpr1
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%1:_(s32) = COPY $sgpr2
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%2:_(s32) = COPY $sgpr3
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%3:_(s32) = G_ATOMIC_CMPXCHG %0, %1, %2 :: (load store seq_cst (s64), addrspace 0)
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...
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