TheRock/compiler/amd-llvm/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.fdot2.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --filter-out "s_wait" --filter-out "s_nop" --filter-out "s_delay_alu" --filter-out "s_setpc_b64"
; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx906 < %s | FileCheck --check-prefixes=GCN,GFX906 %s
; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1011 < %s | FileCheck --check-prefixes=GCN,GFX10 %s
; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1012 < %s | FileCheck --check-prefixes=GCN,GFX10 %s
; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 < %s | FileCheck --check-prefixes=GCN,GFX11 %s

define float @v_fdot2(<2 x half> %a, <2 x half> %b, float %c) {
; GFX906-LABEL: v_fdot2:
; GFX906:  ; %bb.0:
; GFX906:    v_dot2_f32_f16 v0, v0, v1, v2
;
; GFX10-LABEL: v_fdot2:
; GFX10:  ; %bb.0:
; GFX10:    v_dot2c_f32_f16 v2, v0, v1
; GFX10:    v_mov_b32_e32 v0, v2
;
; GFX11-LABEL: v_fdot2:
; GFX11:  ; %bb.0:
; GFX11:    v_dot2acc_f32_f16 v2, v0, v1
; GFX11:    v_mov_b32_e32 v0, v2
  %r = call float @llvm.amdgcn.fdot2(<2 x half> %a, <2 x half> %b, float %c, i1 false)
  ret float %r
}

define float @v_fdot2_clamp(<2 x half> %a, <2 x half> %b, float %c) {
; GCN-LABEL: v_fdot2_clamp:
; GCN:  ; %bb.0:
; GCN:    v_dot2_f32_f16 v0, v0, v1, v2 clamp
  %r = call float @llvm.amdgcn.fdot2(<2 x half> %a, <2 x half> %b, float %c, i1 true)
  ret float %r
}

define float @v_fdot2_neg_a(<2 x half> %a, <2 x half> %b, float %c) {
; GCN-LABEL: v_fdot2_neg_a:
; GCN:  ; %bb.0:
; GCN:    v_dot2_f32_f16 v0, v0, v1, v2 neg_lo:[1,0,0] neg_hi:[1,0,0]
  %neg.a = fneg <2 x half> %a
  %r = call float @llvm.amdgcn.fdot2(<2 x half> %neg.a, <2 x half> %b, float %c, i1 false)
  ret float %r
}

define float @v_fdot2_neg_b(<2 x half> %a, <2 x half> %b, float %c) {
; GCN-LABEL: v_fdot2_neg_b:
; GCN:  ; %bb.0:
; GCN:    v_dot2_f32_f16 v0, v0, v1, v2 neg_lo:[0,1,0] neg_hi:[0,1,0]
  %neg.b = fneg <2 x half> %b
  %r = call float @llvm.amdgcn.fdot2(<2 x half> %a, <2 x half> %neg.b, float %c, i1 false)
  ret float %r
}

define float @v_fdot2_neg_a_neg_b(<2 x half> %a, <2 x half> %b, float %c) {
; GCN-LABEL: v_fdot2_neg_a_neg_b:
; GCN:  ; %bb.0:
; GCN:    v_dot2_f32_f16 v0, v1, v1, v2 neg_lo:[1,1,0] neg_hi:[1,1,0]
  %neg.a = fneg <2 x half> %b
  %neg.b = fneg <2 x half> %b
  %r = call float @llvm.amdgcn.fdot2(<2 x half> %neg.a, <2 x half> %neg.b, float %c, i1 false)
  ret float %r
}

define float @v_fdot2_neg_c(<2 x half> %a, <2 x half> %b, float %c) {
; GCN-LABEL: v_fdot2_neg_c:
; GCN:  ; %bb.0:
; GCN:    v_dot2_f32_f16 v0, v0, v1, v2 neg_lo:[0,0,1]
  %neg.c = fneg float %c
  %r = call float @llvm.amdgcn.fdot2(<2 x half> %a, <2 x half> %b, float %neg.c, i1 false)
  ret float %r
}

define float @v_fdot2_inline_literal_a(<2 x half> %b, float %c) {
; GFX906-LABEL: v_fdot2_inline_literal_a:
; GFX906:  ; %bb.0:
; GFX906:    v_dot2_f32_f16 v0, 2.0, v0, v1 op_sel_hi:[0,1,1]
;
; GFX10-LABEL: v_fdot2_inline_literal_a:
; GFX10:  ; %bb.0:
; GFX10:    v_dot2c_f32_f16 v1, 0x40004000, v0
; GFX10:    v_mov_b32_e32 v0, v1
;
; GFX11-LABEL: v_fdot2_inline_literal_a:
; GFX11:  ; %bb.0:
; GFX11:    v_dot2acc_f32_f16 v1, 0x40004000, v0
; GFX11:    v_mov_b32_e32 v0, v1
  %ret = tail call float @llvm.amdgcn.fdot2(<2 x half> <half 2.0, half 2.0>, <2 x half> %b, float %c, i1 false)
  ret float %ret
}

define float @v_fdot2_inline_literal_b(<2 x half> %a, float %c) {
; GFX906-LABEL: v_fdot2_inline_literal_b:
; GFX906:  ; %bb.0:
; GFX906:    v_dot2_f32_f16 v0, v0, 2.0, v1 op_sel_hi:[1,0,1]
;
; GFX10-LABEL: v_fdot2_inline_literal_b:
; GFX10:  ; %bb.0:
; GFX10:    v_dot2c_f32_f16 v1, 0x40004000, v0
; GFX10:    v_mov_b32_e32 v0, v1
;
; GFX11-LABEL: v_fdot2_inline_literal_b:
; GFX11:  ; %bb.0:
; GFX11:    v_dot2acc_f32_f16 v1, 0x40004000, v0
; GFX11:    v_mov_b32_e32 v0, v1
  %ret = tail call float @llvm.amdgcn.fdot2(<2 x half> %a, <2 x half> <half 2.0, half 2.0>, float %c, i1 false)
  ret float %ret
}

define float @v_fdot2_inline_literal_c(<2 x half> %a, <2 x half> %b) {
; GFX906-LABEL: v_fdot2_inline_literal_c:
; GFX906:  ; %bb.0:
; GFX906:    v_dot2_f32_f16 v0, v0, v1, 1.0
;
; GFX10-LABEL: v_fdot2_inline_literal_c:
; GFX10:  ; %bb.0:
; GFX10:    v_mov_b32_e32 v2, 1.0
; GFX10:    v_dot2c_f32_f16 v2, v0, v1
; GFX10:    v_mov_b32_e32 v0, v2
;
; GFX11-LABEL: v_fdot2_inline_literal_c:
; GFX11:  ; %bb.0:
; GFX11:    v_mov_b32_e32 v2, 1.0
; GFX11:    v_dot2acc_f32_f16 v2, v0, v1
; GFX11:    v_mov_b32_e32 v0, v2
  %ret = tail call float @llvm.amdgcn.fdot2(<2 x half> %a, <2 x half> %b, float 1.0, i1 false)
  ret float %ret
}

define amdgpu_ps float @v_fdot2_sss(<2 x half> inreg %a, <2 x half> inreg %b, float inreg %c) {
; GFX906-LABEL: v_fdot2_sss:
; GFX906:  ; %bb.0:
; GFX906:    v_mov_b32_e32 v0, s1
; GFX906:    v_mov_b32_e32 v1, s2
; GFX906:    v_dot2_f32_f16 v0, s0, v0, v1
; GFX906:    ; return to shader part epilog
;
; GFX10-LABEL: v_fdot2_sss:
; GFX10:  ; %bb.0:
; GFX10:    v_mov_b32_e32 v0, s2
; GFX10:    v_mov_b32_e32 v1, s1
; GFX10:    v_dot2c_f32_f16 v0, s0, v1
; GFX10:    ; return to shader part epilog
;
; GFX11-LABEL: v_fdot2_sss:
; GFX11:  ; %bb.0:
; GFX11:    v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s1
; GFX11:    v_dot2acc_f32_f16 v0, s0, v1
; GFX11:    ; return to shader part epilog
  %r = call float @llvm.amdgcn.fdot2(<2 x half> %a, <2 x half> %b, float %c, i1 false)
  ret float %r
}

declare float @llvm.amdgcn.fdot2(<2 x half>, <2 x half>, float, i1 immarg) #0

attributes #0 = { nounwind readnone speculatable }